Reticle quality and the capability to qualify a reticle remain key issues for EUV Lithography. In this paper, we report on
recent advancements that extend the capability of a 193 nm mask inspector to meet requirements for the 22 nm HP / 15
nm Logic node. This work builds upon previous work that was published earlier this year, by D. Wack1, et. al. Meeting
these requirements requires development of a number of novel capabilities for mask inspection, including the use of offaxis
illumination, various polarization modes, and use of an optimized absorber stack for EUV masks. In addition, we
discuss the challenges of inspecting EUV masks in die-to-database mode, and how tone inversion can be successfully
modeled. Lastly, we show that this same 193 nm mask inspector, with the use of proprietary algorithms, can be
extended to meet industry requirements for EUV phase defect blank inspection.
A new 193nm wavelength high resolution reticle defect inspection platform has been developed for both die-to-database
and die-to-die inspection modes. In its initial configuration, this innovative platform has been designed to meet the
reticle qualification requirements of the IC industry for the 22nm logic and 3xhp memory generations (and shrinks) with
planned extensions to the next generation. The 22nm/3xhp IC generation includes advanced 193nm optical lithography
using conventional RET, advanced computational lithography, and double patterning. Further, EUV pilot line
lithography is beginning. This advanced 193nm inspection platform has world-class performance and the capability to
meet these diverse needs in optical and EUV lithography.
The architecture of the new 193nm inspection platform is described. Die-to-database inspection results are shown on a
variety of reticles from industry sources; these reticles include standard programmed defect test reticles, as well as
advanced optical and EUV product and product-like reticles. Results show high sensitivity and low false and nuisance
detections on complex optical reticle designs and small feature size EUV reticles. A direct comparison with the existing
industry standard 257nm wavelength inspection system shows measurable sensitivity improvement for small feature
sizes
High Resolution reticle inspection is well-established as a proven, effective, and efficient means of detecting yieldlimiting
mask defects as well as defects which are not immediately yield-limiting yet can enable manufacturing process
improvements. Historically, RAPID products have enabled detection of both classes of these defects. The newlydeveloped
Wafer Plane Inspection (WPI) detector technology meets the needs of some advanced mask manufacturers to
identify the lithographically-significant defects while ignoring the other non-lithographically-significant defects. Wafer
Plane Inspection accomplishes this goal by performing defect detection based on a modeled image of how the mask
features would actually print in the photoresist. This has the effect of reducing sensitivity to non-printing defects while
enabling higher sensitivity focused in high MEEF areas where small reticle defects still yield significant printing defects
on wafers.
This approach has several important features. The ability to ignore non-printing defects and to apply additional effective
sensitivity in high MEEF areas enables advanced node development. In addition, the modeling allows the inclusion of
important polarization effects that occur in the resist for high NA operation. This allows for the results to better match
wafer print results compared to alternate approaches. Finally, the simulation easily allows for the application of
arbitrary illumination profiles. With this approach, users of WPI can make use of unique or custom scanner illumination
profiles. This allows the more precise modeling of profiles without inspection system hardware modification or loss of
company intellectual property.
A previous paper [1] introduced WPI in D:D mode. This paper examines the operation and results for WPI in
Die:Database mode.
Wafer Plane Inspection (WPI) is an inspection mode on the KLA-Tencor TeraScaTM platform that uses the high signalto-
noise ratio images from the high numerical aperture microscope, and then models the entire lithographic process to
enable defect detection on the wafer plane[1]. This technology meets the needs of some advanced mask manufacturers
to identify the lithographically-significant defects while ignoring the other non-lithographically-significant defects. WPI
accomplishes this goal by performing defect detection based on a modeled image of how the mask features would
actually print in the photoresist. There are several advantages to this approach: (1) the high fidelity of the images
provide a sensitivity advantage over competing approaches; (2) the ability to perform defect detection on the wafer plane
allows one to only see those defects that have a printing impact on the wafer; (3) the use of modeling on the lithographic
portion of the flow enables unprecedented flexibility to support arbitrary illumination profiles, process-window
inspection in unit time, and combination modes to find both printing and non-printing defects. WPI is proving to be a
valuable addition to the KLA-Tencor detection algorithm suite.
The modeling portion of WPI uses a single resist threshold as the final step in the processing. This has been shown to be
adequate on several advanced customer layers, but is not ideal for all layers. Actual resist chemistry has complicated
processes including acid and base-diffusion and quench that are not consistently well-modeled with a single resist
threshold. We have considered the use of an advanced resist model for WPI, but rejected it because the burdensome
requirements for the calibration of the model were not practical for reticle inspection. This paper describes an alternative
approach that allows for a "soft" resist threshold to be applied that provides a more robust solution for the most
challenging processes. This approach is just finishing beta testing with a customer developing advanced node designs.
High Resolution reticle inspection is well-established as a proven, effective, and efficient means of detecting yield-limiting
mask defects as well as defects which are not immediately yield-limiting yet can enable manufacturing process
improvements. Historically, RAPID products have enabled detection of both classes of these defects. The newly-developed
Wafer Plane Inspection (WPI) detector technology meets the needs of some advanced mask manufacturers to
identify the lithographically-significant defects while ignoring the other non-lithographically-significant defects. Wafer
Plane Inspection accomplishes this goal by performing defect detection based on a modeled image of how the mask
features would actually print in the photoresist. This has the effect of reducing sensitivity to non-printing defects while
enabling higher sensitivity focused in high MEEF areas where small reticle defects still yield significant printing defects
on wafers.
WPI is a new inspection mode that has been developed by KLA-Tencor and is currently under test with multiple
customers. It employs the same transmitted and reflected-light high-resolution images as the industry-standard high-resolution
inspections, but with much more sophisticated processing involved. A rigorous mask pattern recovery
algorithm is used to convert the transmitted and reflected light images into a modeled representation of the reticle.
Lithographic modeling of the scanner is then used to generate an aerial image of the mask. This is followed by resist
modeling to determine the exposure of the photoresist. The defect detectors are then applied on this photoresist plane so
that only printing defects are detected. Note that no hardware modifications to the inspection system are required to
enable this detector. The same tool will be able to perform both our standard High Resolution inspections and the Wafer
Plane Inspection detector.
This approach has several important features. The ability to ignore non-printing defects and to apply additional effective
sensitivity in high MEEF areas enables advanced node development. In addition, the modeling allows the inclusion of
important polarization effects that occur in the resist for high NA operation. This allows for the results to better match
wafer print results compared to alternate approaches. Finally, the simulation easily allows for the application of
arbitrary illumination profiles. With this approach, users of WPI can make use of unique or custom scanner illumination
profiles. This allows the more precise modeling of profiles without inspection system hardware modification or loss of
company intellectual property.
This paper examines WPI in Die:Die mode. Future work includes a review of Die:Database WPI capability.
A new die-to-database high-resolution reticle defect inspection system has been developed for the 45nm logic node and
extendable to the 32nm node (also the comparable memory nodes). These nodes will use predominantly 193nm
immersion lithography although EUV may also be used. According to recent surveys, the predominant reticle types for
the 45nm node are 6% simple tri-tone and COG. Other advanced reticle types may also be used for these nodes
including: dark field alternating, Mask Enhancer, complex tri-tone, high transmission, CPL, EUV, etc. Finally,
aggressive model based OPC will typically be used which will include many small structures such as jogs, serifs, and
SRAF (sub-resolution assist features) with accompanying very small gaps between adjacent structures. The current
generation of inspection systems is inadequate to meet these requirements. The architecture and performance of a new
die-to-database inspection system is described. This new system is designed to inspect the aforementioned reticle types
in die-to-database and die-to-die modes. Recent results from internal testing of the prototype systems are shown. The
results include standard programmed defect test reticles and advanced 45nm and 32nm node reticles from industry
sources. The results show high sensitivity and low false detections being achieved.
The present approach to Optical Proximity Correction (OPC) verification has evolved from a number of separate inspection strategies. OPC decoration is verified by a design rule or optical rule checker, the reticle is verified by a reticle inspection system, and the final wafers are verified by wafer inspection and metrology tools. Each verification step looks at a different representation of the desired device pattern with little or no data flowing between them.
In this paper, we will report on a new inspection system called DesignScan that connects the data between the various abstraction layers. DesignScan inspects the OPC decorated design by simulating how the design will be transferred to the reticle layer and how that reticle will be imaged into resist across the full focus-exposure process window. The simulated images are compared to the desired pattern and defect detection algorithms are applied to determine if any unacceptable variations in the pattern occurs within the nominal process window. The end result is a new paradigm in design verification, moving beyond OPC verification at the design plane to process window verification at the wafer plane where it really matters.
We will demonstrate the application of DesignScan to inspect full chip designs that utilized different Resolution Enhancement Technique (RET) and OPC methods. In doing so, we’ll demonstrate that DesignScan can identify the relative strengths and weaknesses of each methodology by highlighting areas of weak process window for each approach. We will present experimental wafer level results to verify the accuracy of the defect predictions.
Contacts and VIAs are features whose integrity are very susceptible to reticle CD defects or in general, to defects that produce a change of total energy (flux) projected through the reticle. As lithography is extended beyond the 130nm node, the problem becomes more critical. Detecting and analyzing photomask critical dimension (CD) errors and semitransparent defects is vital for qualifying reticles to enable high IC wafer yield for the 90nm node. The current state of the art inspection methods are unable to meet the industry requirements for contact and via features. Using the TeraStarTM pattern inspection system's image computer platform, a new algorithm, TeraFluxTM, has been implemented and tested for the inspection of small 'closed' features. The algorithm compares the transmitted energy flux difference between a test contact (or a group of contacts) and a reference image for small closed features, such as, contacts, trenches, and cells on chrome and half-tone reticles. The algorithm is applicable to both clear and dark field reticles. Sensitivity characterization tests show that the new algorithm provides CD error detection to 6% energy flux variation with low false defect counts. We performed experiments to correlate the sensitivity performance of the new algorithm with wafer printability results. The results will be presented together with results of inspections results of programmed defect plates and production reticles.
With growing implementation of low k1 lithography on DUV scanners for wafer production, detecting and analyzing photomask critical dimension (CD) errors and semitransparent defects is vital for qualifying photomasks to enable high IC wafer yields for 130nm and 100nm nodes. Using the TeraStar pattern inspection system's image computer platform, a new die-to-database algorithm, TeraFlux, has been implemented and tested for the inspection of small "closed" features. The algorithm is run in die-to-database mode comparing the energy flux difference between reticle and the database reference for small closed features, such as, contacts, trenches, and cells on chrome and half-tone reticles. The algorithm is applicable to both clear and dark field reticles. Tests show the new algorithm provides CD error detection to 6% energy flux variation with low false defect counts.
We have characterized the sensitivity and false defect performance of the die-to-database energy flux algorithm with production masks and programmed defect test masks. A sampling of inspection results will be presented. Wafer printability results using the programmed defects on a programmed defect test reticle will be presented and compared to the inspection defect sensitivity results.
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