KEYWORDS: Directed self assembly, Image processing, Signal processing, Electron beam lithography, Lithography, Annealing, Thin films, Epitaxy, Data modeling, 3D modeling
Directed self-assembly (DSA) of block copolymers (BCPs) is a lithographic technique that is expected to be mutually complimentary with ArF immersion lithography, EUV lithography, electron beam direct writing, or nanoimprint for sub-15 nm line patterning and sub-20 nm contact hole patterning. Defect mitigation is the primary challenge behind the use of DSA lithography in practical applications in advanced semiconductor device manufacturing. Therefore, resolve this issue, defect dynamics needs to be clarified using in-situ measurements of self-assembling processes of BCPs in conjunction with modeling approaches.
In this work, the evolution of a surface morphology in self-assembling processes of BCPs during annealing was investigated using in-situ atomic force microscope (AFM).5 A JPK NanoWizard ULTRA Speed AFM (JPK Instruments AG) under AC mode (lock-in phase signal image) was employed to carry out in-situ measurements of self-assembling of symmetrical polystyrene-block-poly(methyl methacrylate) (PS-b-PMMA) thin films with a thickness of 40 nm, and a domain spacing 30 nm domain spacing (L0) of 30 nm on a 5 nm thick neutral layer (PS-r-PMMA) during the thermal annealing process starting from a disordered as-cast state. The COOrdinated Line epitaxy (COOL) process was applied to provide DSA line multiplication patterns as hybrid guide patterns which act as chemical and physical epitaxy process.
The in-situ observation approach of the surface morphology during micro-phase separation process revealed the defect generation and rectification processes in DSA thin films. A combination of the time development data in the in-situ AFM and grazing-incidence small-angle X-ray scattering (GI-SAXS) will also be discussed to develop a kinetic modeling for predicting dynamical changes in the three-dimensional nanostructures.
In this paper we will describe a self-consistent field theory simulation study on bridge defects in lamellae-forming diblock copolymers. Because the bridge defects are buried three-dimensional defects formed in the diblock copolymer film, it is difficult to observe and determine what causes them. To determine the cause of the bridge defects effectively, self-consistent field theory simulations were used. By reproducing structural characteristics of the bridge defects in the simulation, the cause of the bridge defects were clarified. Finally, we discussed ways to prevent the bridge defects.
Directed self-assembly (DSA) of block copolymers (BCPs) has been expected to become one of the most promising next generation lithography candidates for sub-15 nm line patterning and sub-20 nm contact hole patterning. In order to provide the DSA lithography to practical use in advanced semiconductor device manufacturing, defect mitigation in the DSA materials and processes is the primary challenge. We need to clarify the defect generation mechanism using in-situ measurement of self-assembling processes of BCPs in cooperation with modeling approaches to attain the DSA defect mitigation.
In this work, we thus employed in-situ atomic force microscope (AFM) and grazing-incidence small angle X-ray scattering (GI-SAXS) and investigated development of surface morphology as well as internal structure during annealing processes.
Figure 1 shows series of the AFM images of PMAPOSS-b-PTFEMA films during annealing processes. The images clearly show that vitrified sponge-like structure without long-range order in as-spun film transforms into lamellar structure and that the long range order of the lamellar structure increases with annealing temperature. It is well-known that ordering processes of BCPs from disordered state in bulk progress via nucleation and growth. In contrary to the case of bulk, the observed processes seem to be spinodal decomposition. This is because the structure in as-spun film is not the concentration fluctuation of disordered state but the vitrified sponge-like structure. The annealing processes induce order-order transition from non-equilibrium ordered-state to the lamellar structure. The surface tension assists the transition and directs the orientation.
Figure 2 shows scattering patterns of (a) vicinity of film top and (b) whole sample of the GI-SAXS. We can find vertically oriented lamellar structure in the vicinity of film top while horizontally oriented lamellar structures in the vicinity of film bottom, indicating that the GI-SAXS measurement can clarify the variation of the morphologies in depth direction and that the surface tension affects the orientation of the lamellar structure. Finally a combination of the time development data in the in-situ AFM and the GI-SAXS is used to develop a kinetic modeling for prediction of dynamical change in three-dimensional nano-structures.
A part of this work was funded by the New Energy and Industrial Technology Development Organization (NEDO) in Japan under the EIDEC project.
Directed self-assembly (DSA) applying chemical epitaxy is one of the promising lithographic solutions for next generation semiconductor device manufacturing. Especially, DSA lithography using coordinated line epitaxy (COOL) process is obviously one of candidates which could be the first generation of DSA applying PS-b-PMMA block copolymer (BCP) for sub-15nm dense line patterning . DSA can enhance the pitch resolutions, and can mitigate CD errors to the values much smaller than those of the originally exposed guiding patterns. On the other hand, local line placement error often results in a worse value, with distinctive trends depending on the process conditions. To address this issue, we introduce an enhanced measurement technology of DSA line patterns with distinguishing their locations in order to evaluate nature of edge placement and roughness corresponding to individual pattern locations by using images of CD-SEM. Additionally correlations among edge roughness of each line and each space are evaluated and discussed. This method can visualize features of complicated roughness easily to control COOL process. As a result, we found the followings. (1) Line placement error and line placement roughness of DSA were slightly different each other depending on their relative position to the chemical guide patterns. (2) In middle frequency area of PSD (Power Spectral Density) analysis graphs, it was observed that shapes were sensitively changed by process conditions of chemical stripe guide size and anneals temperature. (3) Correlation coefficient analysis using PSD was able to clarify characteristics of latent defect corresponding to physical and chemical property of BCP materials.
Si-rich poly((polyhedral oligomeric silsesquioxane) methacrylate)-b-poly(trifluoroethyl methacrylate) (PMAPOSS-b- PTFEMA) was used to form 8-nm half-pitch line and space (L/S) pattern via grapho-epitaxy. Vertical alignment of the lamellae was achieved without using either a neutral layer or top-coating material. Because PMAPOSS-b-PTFEMA forms vertical lamellae on a variety of substrates, we used two types of physical guide structures for grapho-epitaxy; one was a substrate guide and the other was a guide with an embedded under layer. On the substrate guide structure, a fine L/S pattern was obtained with trench widths equal to 3–7 periods of the lamella spacing of the block copolymer, Lo. However, on the embedded under layer guide structure, L/S pattern was observed only with 3 Lo and 4 Lo in trench width. Cross-sectional transmission electron microscope images revealed that a thick PMAPOSS layer was formed under the PMAPOSS-b-PTFEMA L/S pattern. Pattern transfer of the PMAPOSS-b-PTFEMA L/S pattern was prevented by a thick PMAPOSS layer. To achieve pattern transfer to the under layer, optimization of the surface properties is necessary.
Our target at EIDEC is to study the feasibility of directed self-assembly (DSA) technology for semiconductor device manufacturing through electrical yield verification by development of such as process, material, metrology, simulation and design for DSA. We previously developed a grapho/chemo-hybrid coordinated line epitaxial process for sub-15-nm line-and-space (L/S) patterning using polystyrene-block-poly(methyl methacrylate) lamellar block copolymers (BCPs)1– 3. Electrical yield verification results showed that a 30% open yield was successfully achieved with a metal wire line length of 700 μm 4. In the next stage of the evaluation, a sub-10-nm L/S DSA patterning process based on graphoepitaxial DSA of 20-nm lamellar period organic BCPs was developed based on neutral layer and guide space width optimization. At a 30-nm guide height, problems such as BCP overflow and DSA line shorts were observed after the dry development. At a 60-nm guide height, grid-like short defects were observed under dry development shallow etch conditions and sub-10-nm L/S patterns were formed under optimized etch conditions with a suitable BCP film thickness margin. The process performance was evaluated in terms of defects and critical dimension measurements using an electron beam inspection system and critical dimension-scanning electron microscope metrology. The main DSA defects were short defects, and the spatial roughness appeared to be caused by the periodic pitches of these short defects and the guide roughness. We successfully demonstrated the fabrication of sub-10-nm metal wires consists of L/S, pad, connect and cut patterns with controlled alignment and stack structure through lithography, etching and CMP process on a 300- mm wafer using the fully integrated DSA process and damascene processing.
Directed self-assembly is a candidate process for sub-15-nm patterning applications. It will be necessary to develop the DSA process fully and consider process integration to adapt the DSA process for use in semiconductor manufacturing. We investigated the reactive ion etching (RIE) process for the fabrication of sub-10-nm metal wires using the DSA process and the process integration requirements for electrical yield verification. We evaluated the process using an organic high-chi block copolymer (BCP) with a lamellar structure. One critical issue during DSA pattern transfer involves the BCP bottom connection. The BCP bottom connections could be removed without BCP mask loss by using the optimum bias power and the optimum BCP film thickness. The sub-10-nm DSA line-and-space (L/S) patterns were successfully transferred to a SiO2 layer with sufficient film thickness for the fabrication of the metal wire. We also evaluated the overlay technique used in the process. The connect patterns and cut patterns were overlaid on 10-nm trenches fabricated by the DSA process.
The perpendicularly orientated lamellar structure of the self-organized diblock copolymer is an attractive template for sub-10-nm line-and-space pattern formation. We propose a method of evaluating the neutral layer (NL) whose performance has an important bearing on the perpendicular orientation of the lamellar structure. The random copolymer of methyl methacrylate and i-butyl POSS methacrylate (MAIBPOSS) has been investigated as an NL for a polymethylmethacrylate-b-polymethacrylethylPOSS (PMMA-b-PMAIBPOSS) lamellar structure. PMMA-b-PMAIBPOSS material has the potential to form sub-10 nm line-and-space pattern, in addition to high etch selectivity due to its POSS structure. Under the free surface, PMMA-b-PMAIBPOSS film on the random copolymer layer showed horizontal orientation. However, a half-pitch of a 7-nm finger pattern structure was observed by peeling off the horizontally oriented layer. The upper portion of the PMMA-b-PMAIBPOSS film was eliminated till proximity of the random copolymer layer by CF4 gas etching. From the result, it was revealed that the PMMA-r-PMAIBPOSS works as an NL. It was confirmed that the contact angle analysis using an appropriate polymer is a suitable method for evaluation of the surface energy performance of the copolymer with the attribute of high segregation energy.
In this study, half-pitch (HP) 15 nm line-and-space (L/S) metal wires were successfully fabricated and fully integrated on a 300 mm wafer by applying directed self-assembly (DSA) lithography and pattern transfer for semiconductor device manufacturing. In order to evaluate process performances of DSA, we developed a simple sub-15 nm L/S patterning process using polystyrene-block-poly(methyl methacrylate) (PS-b-PMMA) lamellar block copolymer (BCP), which utilizes trimming resist and shallow etching spin-on-glass (SOG) as pinning guide[1]-[4]. From the results of defect inspection after SOG etch using Electron Beam (EB) inspection system, defects were classified as typical DSA defects or defects relating to DSA pattern transfer. From the evaluation of DSA L/S pattern Critical Dimension (CD), roughness and local placement error using CD-SEM, it is considered that isolated PS lines are placed at the centerline between guides and that placement of paired PS lines depends on the guide width. The control of the guide resist CD is the key to local placement error and the paired lines adjacent to the guide shifted toward the outside (0.5 nm) along the centerline of the isolated line after SOG etch. We demonstrated fabrication of HP 15 nm metal wires in trenches formed by the DSA process with reactive ion etching (RIE), followed by metal chemical vapor deposition (CVD) and chemical mechanical polishing (CMP). By SEM observation of alignment errors between the trenches and connect spaces, overlay shift patterns (-4 nm) in guide lithography mask were fabricated without intra-wafer alignment errors.
Directed self-assembly (DSA) is one of the promising candidates for next-generation lithography. We developed a novel simple sub-15 nm line-and-space (L/S) patterning process, the “coordinated line epitaxy (COOL) process,” using grapho- and chemo-hybrid epitaxy. In this study we evaluate the DSA L/S pattern transfer margin. Since defect reduction is difficult in the case of the DSA pattern transfer process, there is a need to increase the pattern transfer margin. We also describe process integration for electrical yield verification.
We proposed a new concept of “defect-aware process margin.” Defect-aware process margin was evaluated by investigating the energy difference between the free-energy of the most stable state and that of the first metastable state. The energy difference is strongly related to the defect density in DSA process. As a result of our rigorous simulations, the process margin of the pinning layer width was found to be: (1) worse when the pinning layer affinity is too large, (2) better when the background affinity has the opposite sign of the pinning layer affinity, and (3) better when the top of the background layer is higher than that of the pinning layer by 0.1L0.
A contact hole shrink process using directed self-assembly lithography (DSAL) for sub-30 nm contact hole patterning is reported on. DSAL using graphoepitaxy and poly (styrene-block-methyl methacrylate) (PS-b -PMMA) a block copolymer (BCP) was demonstrated and characteristics of our process are spin-on-carbon prepattern and wet development. Feasibility of DSAL for semiconductor device manufacturing was investigated in terms of DSAL process window. Wet development process was optimized first; then critical dimension (CD) tolerance of prepattern was evaluated from three different aspects, which are DSA hole CD, contact edge roughness (CER), and hole open yield. Within 70+/−5 nm hole prepattern CD, 99.3% hole open yield was obtained and CD tolerance was 10 nm. Matching between polymer size and prepattern size is critical, because thick PS residual layer appears at the hole bottom when the prepattern holes are too small or too large and results in missing holes after pattern transfer. We verified the DSAL process on a 300-mm wafer at target prepattern CD and succeeded in patterning sub-30 nm holes on center, middle, and edge of wafer. Average prepattern CD of 72 nm could be shrunk uniformly to DSA hole pattern of 28.5 nm. By the DSAL process, CD uniformity was greatly improved from 7.6 to 1.4 nm, and CER was also improved from 3.9 to 0.73 nm. Those values represent typical DSAL rectification characteristics and are significant for semiconductor manufacturing. It is clearly demonstrated that the contact hole shrink using DSAL is a promising patterning method for next-generation lithography.
Dissipative particle dynamics (DPD) simulations are utilized to optimize contact hole shrink process using
graphoepitaxial directed self-assembly (DSA). In this work, poly (styrene-block-methyl methacrylate) (PS-b-PMMA)
was employed. In the contact hole shrink process, PS residual layer was formed on the bottom floor of the hole type prepattern.
To realize reliable contact hole shrink process, minimization of the thickness of PS residual layer was one of the
key issues. It was found that the minimization of the thickness of the PS residual layer and optimization of threedimensional
configuration of the PMMA domain was trade-off relationship. By using DPD simulations, the parameters
were successfully optimized to achieve residual layer free contact hole shrink of DSA lithography.
Directed self-assembly lithography (DSAL), which combines self-assembling materials and a lithographically
defined prepattern, is a potential candidate to extend optical lithography beyond 22 nm. To take full
advantage of DSAL requires diminishing not only systematic error modes but also random error modes by
carefully designing a lithographically defined prepattern and precisely adjusting process conditions. To
accomplish this with satisfactory accuracy, we have proposed a novel method to evaluate DSAL error modes
based on simulations using dissipative particle dynamics (DPD). We have found that we can estimate not only
systematic errors but also random errors qualitatively by simulations.
A method for using wet development in a directed self-assembly lithography (DSAL) application is reported. For the typical diblock copolymer poly(styrene-block-methyl methacrylate) (PS-b-PMMA), the PMMA area is removed by an oxygen plasma. However, the oxygen plasma has poor selectivity for the PS portion of the block polymer and etches it simultaneously. As a result, the thickness of the residual PS pattern is thinner than desired and creates a challenge for subsequent pattern transfer. A wet development technique is discussed which offers higher selectivity between the PMMA and PS blocks in the assembled pattern. Specifically, a method using a low pressure mercury lamp and conventional tetramethylammonium hydroxide (TMAH, 2.38%) developer is proposed. Using this method, DSA pattern formation is completed in a single track having coating, baking, exposure, and development modules.
KEYWORDS: Deep ultraviolet, Polymethylmethacrylate, Photoresist developing, Picosecond phenomena, Photoresist materials, Scanning electron microscopy, Lithography, System on a chip, Photomicroscopy, Directed self assembly
We report on a contact hole shrink process using directed self-assembly. A diblock copolymer, poly (styrene-blockmethyl
methacrylate) (PS-b-PMMA), is used to shrink contact holes. Contact hole guide patterns for graphoepitaxy are
formed by ArF photoresists. Cylindrical domains of PMMA is removed using organic solvents after DUV (λ <200 nm)
irradiation. In this work, it is found that a solvent system is the best developer from the evaluated single solvent systems
and mixed solvent systems. The wet development of PS-b-PMMA strongly depends on total exposure dose of DUV
irradiation. With lower exposure dose, the cylindrical domains of PMMA are not clearly removed. With optimum
exposure dose, PMMA is developed clearly. The contact hole guide patterns of 75 nm in diameter are successfully
shrunk to 20 nm in diameter using the wet development process.
We report wet development technique for directed self-assembly lithography pattern. For typical diblock copolymer,
poly (styrene-block-methyl methacrylate) (PS-b-PMMA), the PMMA area is removed by O2 plasma. However, O2 plasma attack also etches off PS area simultaneously. As a result, the thickness of residual PS pattern is thinner and it
causes degradation of PS mask performance. PS thickness loss in the device integration is not desirable as etching mask
role. In this work, we applied wet development technique which could be higher selectivity to keep PS film thickness
after pattern formation. Especially, we propose the method using low pressure mercury lamp and conventional TMAH
(2.38%) as developer. It is expected to accomplish pattern formation in one track with coating, baking, exposure and
development.
Resist process challenges for 32-nm node and beyond are discussed in this paper. For line and space (L/S) logic patterns,
we examine ways to balance the requirements of resolution-enhancement techniques (RETs). In 32-nm node logic
patterning, two-dimensional (2D) layout pattern deformation becomes more severe with stronger RET (e.g., narrow
angle CQUAD illumination). Also pattern collapse more frequently happens in 2D-pattern layouts when stronger RET is
used. In contrast, milder RET (annular illumination) does not induce the severe pattern collapse in 2D-pattern layout. For
2D-pattern layouts, stronger RET seems to worsen image contrast and results in high background-light in the resist
pattern, which induces more pattern collapse. For the minimum-pitch L/S pattern in 32-nm node logic, annular
illumination is acceptable for patterning with NA1.35 scanner when high contrast resist is used. For contact/via patterns,
it is necessary to expand the overlapping CD process window. Better process margin is realized through the combination
of hole-shrink technique and precise acid-diffusion control in an ArF chemically amplified resist.
We have designed the lithography process for 28nm node logic devices using 1.35NA scanner. In the
28nm node, we face on the ultra-low k1 lithography in which dense pattern is affected by the mask
topography effect and the oblique-incidence. Using the rigorous lithography simulation considering
the electro-magnetic field, we have estimated accurately the feasibility of resolution of the minimum
pitch required in 28nm node. The optimum mask plate and illumination conditions have been
decided by simulation. The experimental results for 28nm node show that the minimum pitch
patterns and minimum SRAM cell are clearly resolved by single exposure.
We have developed the lithography process for 32nm node logic devices under the 1.35NA single-exposure conditions. In low-k1 generation, we have to consider the minimum pitch resolution and two-dimensional pattern fidelity at the same time. Although strong RET (Resonance Enhancement Technique) can achieve the high image contrast, it has negative effects like line end shortening and resist pattern collapse. Moderate RET such as annular illumination can combine the minimum pitch resolution and two-dimensional pattern fidelity with hyper NA illumination condition. The simulation and experimental results indicate that the minimum pitches should be determined as 100nm for line pattern and 110nm for contact hole pattern, respectively. The isolated contact hole needs SRAF and focus drift exposure to improve DOF. Embedded SRAM cell of 0.125&mgr;m2 area is clearly resolved across exposure and focus window.
Key issues of resist process design for 32nm node logic device were discussed in this paper. One of them is reflectivity
control in higher 1.3NA regime. The spec for the reflectivity control is more and more severe as technology node
advances. The target of reflectivity control over existent substrate thickness variation is 0.4%, which was estimated from
our dose budget analysis. Then, single BARC process or stacked mask process (SMAP) was selected to each of the
critical layers according to the substrate transparency. Another key issue in terms of material process was described in
this paper, that is spin-on-carbon (SOC) pattern deformation during substrate etch process. New SOC material without
any deformation during etch process was successfully developed for 32nm node stacked mask process (SMAP). 1.3NA
immersion lithography and pattern transfer performance using single BARC
KEYWORDS: System on a chip, Etching, Reactive ion etching, Reflectivity, Hydrogen, Fluorine, Lithography, Photoresist processing, Silica, Scanning electron microscopy
The stacked-mask process (S-MAP) is a tri-level resist process by lithography and dry etching, which consists of thin
resist, spin-on-glass (SOG), and spun-on carbon (SOC). However, as design rules progress below 60nm, two problems
arise in the conventional S-MAP: 1) the deformation of SOC line pattern during SiO2 reactive ion etching (RIE), 2) the
degradation of lithography performance due to high reflectivity at the interface between resist and SOG in high NA. In
this study, we clarified the origin of the above problems and improved S-MAP materials and processes. Firstly, we
found that the pattern deformation is induced by the inner stress due to volume expansion by fluorination during RIE,
and that the deformation is suppressed by decreasing hydrogen content of SOC. Secondly, we developed new carbon-containing
SOG that coexists with low reflectivity and acceptable etching performance. Using the above SOG and SOC,
we developed a new S-MAP that shows an excellent lithography / etching performance in sub-45nm device fabrication.
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