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As chip feature sizes have continued to shrink, resolution enhancement techniques such as Optical Proximity Correction (OPC) have been utilized in advanced technology nodes. In recent years, Inverse Lithography Technology (ILT), a new OPC technique, has been widely applied in advanced Logic and Memory applications to improve imaging performance. Compared to the conventional OPC, ILT enables better process windows (PW) with low edge placement error (EPE) and high wafer critical dimension uniformity (CDU), etc. However, the nonrectilinear mask shapes in ILT make mask writing extremely complex and slow, which can potentially cause more mask manufacturing errors. Therefore, it’s important to quantitatively study the MEEF in ILT masks. In this work, we studied the MEEFs of 2D patterns corrected by ILT and conventional OPC and the differences between these two techniques. The results show that the MEEF at different positions (local MEEF) on an ILT mask has a bigger mean of ~3.14 and a smaller σ of ~0.09 relative to the mean of ~2.14 and σ of ~0.67 from a conventional OPC mask. The MEEF budget is analyzed based on the separated main features (MF) and subresolution assist features (SRAF). With SRAFs being inserted into the entire layout of the ILT mask, it contributes to all individual patterns with ~ 45% (1.49) of the total MEEF. Meanwhile, a conventional OPC mask only has SRAFs on the edges. Thus, SRAFs only contribute MEEF to the patterns located in the edge region (within the proximity effect range). Thus, the main center region of the OPC Mask has a lower MEEF contribution (~1.7). These results suggest that in the ILT recipe tuning process, MEEF should also be included in the cost function as a nonlinear factor so that the inversion can minimize MEEF while optimizing PW and EPE. Furthermore, the manhattanization of the ILT Mask can effectively reduce MEEF.
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