Pair-match Huffman transcoding to achieve a highly parallel variable-length decoder with two-word bit stream segmentation

Michael Bakhmutsky

doi:10.1117/12.263517

17 January 1997 Pair-match Huffman transcoding to achieve a highly parallel variable-length decoder with two-word bit stream segmentation

Michael Bakhmutsky

Author Affiliations +

Proceedings Volume 3021, Multimedia Hardware Architectures 1997; (1997) https://doi.org/10.1117/12.263517
Event: Electronic Imaging '97, 1997, San Jose, CA, United States

Abstract

An MPEG-2 Main Profile, high level compliant HDTV video decoder requires a variable length decoder (VLD) that can decode macroblocks at rates exceeding 100 million code words per second. The implementation of a high-performance VLD for such an application presents a major challenge in architecture design. The capability of the VLD to process macroblocks in real-time can reduce system memory requirements and simplify decoder architectures. It is more desirable to conceive of a 'one-piece' VLD capable of operating with minimal logic and memory resources and in real-time. Parallel partitioning of the video decoder on the VLD level increases the overall complexity and memory utilization. The two-word bit stream segmentation method developed by Philips Research -- USA achieves high performance without the expense of high hardware complexity or the addition of extra system memory. In this respect, this VLD implementation is very suitable for consumer digital HDTV video decoders. However, the performance guarantee of this architecture is associated with carefully specified statistical tradeoffs. The described method of pair-mach Huffman transcoding provides the VLD performance guarantee on a macroblock level without any statistical tradeoffs. Applied to the main body of the bit stream, this method produces excellent performance results for both consumer and professional MPEG profiles.

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Michael Bakhmutsky "Pair-match Huffman transcoding to achieve a highly parallel variable-length decoder with two-word bit stream segmentation", Proc. SPIE 3021, Multimedia Hardware Architectures 1997, (17 January 1997); https://doi.org/10.1117/12.263517

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