Flagged prefix adder for dual additions

Neil Burgess

doi:10.1117/12.325715

2 October 1998 Flagged prefix adder for dual additions

Neil Burgess

Proceedings Volume 3461, Advanced Signal Processing Algorithms, Architectures, and Implementations VIII; (1998) https://doi.org/10.1117/12.325715
Event: SPIE's International Symposium on Optical Science, Engineering, and Instrumentation, 1998, San Diego, CA, United States

Abstract

This paper describes how a w-bit prefix-type carry-lookahead adder may be modified to yield more than one result per operation. The modified adder, called a 'flagged prefix adder', adds two 2's-complement numbers to give a sum S equals A + B but returns anyone of the following results: S; S + 1; -(S + 1); -(S + 2) as a function of a set of flag bits derived by the adder concurrently with the addition. Similarly, if the flagged prefix adder preforms the 2's-complement subtraction S equals A-B, the adder may return any one of: S, S- 1, -S, -(S + 1). Hence, the flagged prefix adder may be used to perform 'instant increment' or 'instant complement' operations. The extra logic required by the flagged prefix adder relative to the original prefix adder is 2w gates and w 2-to-1 multiplexers.

Citation Download Citation

Neil Burgess "Flagged prefix adder for dual additions", Proc. SPIE 3461, Advanced Signal Processing Algorithms, Architectures, and Implementations VIII, (2 October 1998); https://doi.org/10.1117/12.325715

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