Reticle enhancement verification for the 65nm and 45nm nodes

Kevin Lucas; Kyle Patterson; Robert Boone; Corinne Miramond; Amandine Borjon; Jerome Belledent; Olivier Toublan; Jorge Entradas; Yorick Trouiller

doi:10.1117/12.658823

14 March 2006 Reticle enhancement verification for the 65nm and 45nm nodes

Kevin Lucas, Kyle Patterson, Robert Boone, Corinne Miramond, Amandine Borjon, Jerome Belledent, Olivier Toublan, Jorge Entradas, Yorick Trouiller

Author Affiliations +

Proceedings Volume 6156, Design and Process Integration for Microelectronic Manufacturing IV; 61560R (2006) https://doi.org/10.1117/12.658823
Event: SPIE 31st International Symposium on Advanced Lithography, 2006, San Jose, California, United States

Abstract

In the last 2 years, the semiconductor industry has recognized the critical importance of verification for optical proximity correction (OPC) and reticle/resolution enhancement technology (RET). Consequently, RET verification usage has increased and improved dramatically. These changes are due to the arrival of new verification tools, new companies, new requirements and new awareness by product groups about the necessity of RET verification. Currently, as the 65nm device generation comes into full production and the 45nm generation starts full development, companies now have the tools and experience (i.e., long lists of previous errors to avoid) needed to perform a detailed analysis of what is required for 45nm and 65nm RET verification. In previous work [1] we performed a theoretical analysis of OPC & RET verification requirements for the 65nm and 45nm device generations and drew conclusions for the ideal verification strategy. In this paper, we extend the previous work to include actual observed verification issues and experimental results. We analyze the historical experimental issues with regard to cause, impact and optimum verification detection strategy. The results of this experimental analysis are compared to the theoretical results, with differences and agreement noted. Finally, we use theoretical and experimental results to propose an optimized RET verification strategy to meet the user requirements of 45nm development and the differing requirements of 65nm volume production.

Citation Download Citation

Kevin Lucas, Kyle Patterson, Robert Boone, Corinne Miramond, Amandine Borjon, Jerome Belledent, Olivier Toublan, Jorge Entradas, and Yorick Trouiller "Reticle enhancement verification for the 65nm and 45nm nodes", Proc. SPIE 6156, Design and Process Integration for Microelectronic Manufacturing IV, 61560R (14 March 2006); https://doi.org/10.1117/12.658823

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