Implementing and validating double patterning in 22-nm to 16-nm product design and patterning flows

Myung-Soo Noh; Beom-Seok Seo; Suk-Joo Lee; Alex Miloslavsky; Christopher Cork; Levi Barnes; Kevin Lucas

doi:10.1117/12.848194

3 March 2010 Implementing and validating double patterning in 22-nm to 16-nm product design and patterning flows

Myung-Soo Noh, Beom-Seok Seo, Suk-Joo Lee, Alex Miloslavsky, Christopher Cork, Levi Barnes, Kevin Lucas

Proceedings Volume 7640, Optical Microlithography XXIII; 76400S (2010) https://doi.org/10.1117/12.848194
Event: SPIE Advanced Lithography, 2010, San Jose, California, United States

Abstract

In double-patterning technology (DPT), we study the complex interactions of layout creation, physical design and design rule checking flows for the 22nm and 16nm device nodes. Decomposition includes the cutting (splitting) of original design-intent features into new overlapping polygons where required; and the coloring of all the resulting polygons into two mask layouts. We discuss the advantages of geometric distribution for polygon operations with the limited range of influence. Further, we find that even the naturally global coloring step can be handled in a geometrically local manner. We analyze and compare the latest methods for designing, processing and verifying DPT methods including the 22nm and 16nm nodes.

Citation Download Citation

Myung-Soo Noh, Beom-Seok Seo, Suk-Joo Lee, Alex Miloslavsky, Christopher Cork, Levi Barnes, and Kevin Lucas "Implementing and validating double patterning in 22-nm to 16-nm product design and patterning flows", Proc. SPIE 7640, Optical Microlithography XXIII, 76400S (3 March 2010); https://doi.org/10.1117/12.848194

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