This paper presents the performance evaluation of a unique method called heating based resistance nonuniformity
compensation (HB-RNUC). The HB-RNUC method utilizes a configurable bias heating duration for each pixel in order
to minimize the readout integrated circuit (ROIC) output voltage distribution range. The outputs of each individual pixel
in a resistive type microbolometer differ from each other by a certain amount due to the resistance non-uniformity
throughout the focal plane array (FPA), which is an inevitable result of the microfabrication process. This output
distribution consumes a considerable portion of the available voltage headroom of the ROIC unless compensated
properly. The conventional compensation method is using on-chip DACs to apply specific bias voltages to each pixel
such that the output distribution is confined around a certain point. However, on-chip DACs typically occupy large
silicon area, increase the output noise, and consume high power. The HB-RNUC method proposes modifying the
resistances of the pixels instead of the bias voltages, and this task can be accomplished by very simple circuit blocks.
The simplicity of the required blocks allows utilizing a low power, low noise, and high resolution resistance nonuniformity
compensation operation. A 9-bit HB-RNUC structure has been designed, fabricated, and tested on a 384x288
microbolometer FPA ROIC on which 35μm pixel size detectors are monolithically implemented, in order to evaluate its
performance. The compensation operation reduces the standard deviation of the ROIC output distribution from 470 mV
to 9 mV under the same readout gain and bias settings. The analog heating channels of the HB-RNUC block dissipate
around 4.1 mW electrical power in this condition, and the increase in the output noise due to these blocks is lower than
10%.
This paper introduces a detector biasing scheme proper for resistive microbolometer type uncooled thermal detector focal
plane arrays (FPAs). The proposed scheme utilizes a 2-stage digital-to-analog converter (DAC) architecture where the first
DAC stage generates the voltage interval that covers the bias voltage range of the overall FPA, while the second stage
generates the high resolution analog voltages that are used to apply pixel-specific bias voltages. The second DAC stage
output includes a resistive ladder type multi-level voltage generator (MLVG), which can be shared by multiple column
readouts. The proposed scheme utilizes a single first stage DAC and a number of second stage DACs that can be optimized
to meet the specifications of the application. The proposed scheme provides high resolution bias correction with small
silicon area coverage, low power dissipation, and low noise. Furthermore, this scheme is suitable for microbolometer FPAs
with very different detector resistance ranges, since the bias correction voltage interval is adjustable by the first DAC stage.
The proposed architecture is used to design a 5+5 bit, 2-stage DAC that can be used in a 640x480 microbolometer FPA
where a standard 0.35 μm CMOS process is considered. The simulation results show that the circuit provides a detector
current resolution of 130 nA when the architecture is optimized to cover a 80 kΩ nominal detector resistance with ±10%
resistance nonuniformity. The designed circuit dissipates 7.5 mW with a single 5 V supply, and the noise contribution to
the detector current is 30 pA for a 10 kHz electrical bandwidth.
This paper presents a column-based, two-stage, 12-bit analog-to-digital converter structure designed for uncooled
microbolometer arrays. On-chip analog-to-digital converters prevent the degradation of sensitive analog output by
external noise sources as well as providing a more integrated functionality. Despite these advantages, the area and power
constraints limit the usage of high performance converters. This paper presents a new structure that provides a balance
between area, power, and performance. The structure is composed of two stages: a tracking ADC stage running at each
column during integration and a successive approximation ADC stage which is shared by a number of columns
depending on the array size and operation frequency. The tracking ADC operates during the integration time, while the
second ADC starts after the integration is completed. The converter includes self-calibration to lower the effect of
process variations and digital correction mechanisms to eliminate the need for low-offset comparators. The simulations
and theoretical calculations based on the simulation results show that the total power dissipation of the proposed
structure will be approximately 73.7 mW and 88.4 mW on a 320x240 array operating at 60 Hz and 384x288 array
operating at 50 Hz, respectively.
KEYWORDS: Staring arrays, Capacitance, Multiplexing, Sensors, Microbolometers, Switches, Digital electronics, Temperature metrology, Signal processing, Metals
This paper presents a new, low power readout circuit approach for uncooled resistive microbolometer FPAs. The
readout circuits of the microbolometer detectors contain parallel readout channels whose outputs are driven and
multiplexed on large bus capacitances in order to form the output of the readout circuit. High number of opamps used in
the readout channel array and large output capacitances that these opamps should drive necessitates the use of high
output current capacity structures, which results in large power dissipation. This paper proposes two new methods in
order to decrease the power dissipation of the readout circuits for uncooled thermal FPAs. The first method is called the
readout channel group concept, where the readout channel array is separated into groups in order to decrease the load
capacitance seen by the readout channel output. The second method utilizes a special opamp architecture where the
output current driving capacity can be digitally controlled. This method enables efficient use of power by activating the
high output current driving capacity only during the output multiplexing. The simulations show that using these
methods results in a power dissipation reduction of 80% and 91% for the readout channels optimized for a single output
384x288 FPA operating at 25 fps and for a two-output 640x480 FPA operating at 30 fps, respectively.
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