The future CMOS generations for microelectronics will require advanced doping techniques capable to realize ultra-shallow, highly-doped junctions with abrupt profiles. Recent experiments have shown the potential capabilities of laser processing of Ultra Shallow Junctions (USJ). According to the International Technology Roadmap for Semiconductors, two laser processes are able to reach ultimate predictions: laser thermal processing or annealing (LTP or LTA) and Gas Immersion Laser Doping (GILD). Both processes are based on rapid melting/solidification of the substrate. During solidification, the liquid silicon, which contains the dopants, is formed epitaxially from the underlying crystalline silicon. In the case of laser thermal annealing dopants are implanted before laser processing. GILD skips the ion-implantation step: in this case dopants are chemisorbed on the Si surface before the laser shot. The dopants are then incorporated and activated during the laser process. Activation is limited to the liquid layer and this chemisorption/laser shot cycle can be repeated until the desired concentration is reached. In this paper, we investigate the possibilities and limitations of the GILD technique for two different substrates: silicon bulk and SOI. We also show some laser doping applications for the fabrication of micro and nanoresonators, widely used in the MEMS Industry.
The goal of this paper is to understand the optical phenomena at dielectric levels (contact, local interconnect, via and damascene line levels). The purpose is also to quantify the impact of dielectric and resist thickness variations on the CD range with and without Bottom Anti Reflective Coating (BARC). First we will show how all dielectric levels can be reduced to the stack metal/oxide/BARC/resist, and what are the contributions to resist and dielectric thickness range for each levels. Then a simple model will be developed to understand CD variation in this stack: by extending the Perot-Fabry model to the dielectric levels, developed by Brunner for the gate level, we can obtain a simple relation between the CD variation and all parameters (metal, oxide thickness, resist thickness, BARC absorbency). Experimentally CD variations for damascene line level on 0.18 micrometers technology has been measured depending on oxide thickness and resist thickness and can confirm this model. UV5 resist, AR2 BARC from Shipley and Top ARC from JSR have been used for these experiments.
The goal of this paper is to understand the optical phenomena at dielectric levels. The purpose is also to quantify the impact of dielectric and resist thickness variations on the CD range with and without Bottom Anti Reflective COating (BARC). First we will show how all dielectric levels can be reduced to the stack metal/oxide/BARC/resist, and what are the contributions to resists and dielectric thickness range for each levels. Then a simple model will be developed to understand CD variation in this tack: by extending the Perot/Fabry model to the dielectric levels, developed by Brunner for the gate level, we can obtain a simple relation between the CD variation and all parameters. Experimentally CD variation for Damascene line level on 0.18micrometers technology has been measured depending on oxide thickness and resist thickness and can confirm this model. UV5 resist, AR2 BARC from Shipley and Top ARC from JSR have been used for these experiments. The main conclusions are: (1) Depending on your dielectric deposition and CMP processes, if resist thickness is controlled, a standard BARC process used for the gate is adapted to remove oxide thickness variation influence providing the optimized resist thickness is used. (2) If both resist thickness and dielectric thickness are uncontrolled, a more absorbent BARC is required.
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