Future Multi-Domain Operations (MDO) will require the coordination of hundreds, even thousands, of devices and component services. This will demand the capability to rapidly discover the distributed devices/services and combine them into different work ow configurations, thereby creating the applications necessary to support changing mission needs. To meet these objectives, we envision a distributed Cognitive Computing System (CCS) that consists of humans and software that work together as a ‘Distributed Federated Brain'. Motivated by neuromorphic processing models, we present an approach that uses hyper-dimensional symbolic semantic vector representations of the services/devices and workflows. We show how these can be used to perform decentralized service/device discovery and work ow composition in the context of a dynamic communications re-planning scenario. In this paper, we describe how emerging analogue AI ‘In Memory' and ‘Near Memory' computing devices can be used to efficiently perform some of the required hyper-dimensional vector computation (HDC). We present an evaluation of the performance of an energy-efficient phase change memory device (PCM) that can perform the required vector operations and discuss how such devices could be used in energy-critical ‘edge of network' tactical MDO operations.
High leakage current in deep submicron regime is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are scaled every technology generation. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low power applications. This paper considers various transistor intrinsic leakage mechanisms including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, gate oxide tunneling, and bad-to-band-tunneling and explores different techniques to reduce leakage power consumption for scaled technologies.
Conference Committee Involvement (2)
VLSI Circuits and Systems II
9 May 2005 | Sevilla, Spain
VLSI Circuits and Systems
19 May 2003 | Maspalomas, Gran Canaria, Canary Islands, Spain
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