The shrinking of device critical dimensions (CD) requires tighter control of critical dimension uniformity with every new device node. For propagating CD sampling recipes from process development to high-volume manufacturing (HVM), the number of sampled sites needs to be reduced. One of the largest challenges is the optimization of the measurement sample plan without sacrificing fingerprint quality. We developed a sampling optimization module that can predict the impact of CD downsampling on model quality and variability. Two modes of sampling optimization have been evaluated: rule-based (maximizing distances between sites) and data-based (keeping specific CD signatures intact). The optimized sampling plans can be exported or used inside the process control and monitoring software (OVALiS) to down-sample existing dense measurements and verify the performance on unseen datasets. We can rigorously simulate the effect of reduced sampling on CD dose correction and CDU control.
We developed a statistical method that can be applied to overlay metrology tools to improve performance and time-to-results (TTR) of multi-cycle optimization based on the brute force method. First, we evaluated full response surfaces for each combination of the discrete equipment settings and calculated desirability scores using a normalization function. Second, we combined gradient optimization techniques and response surface methodologies to find the important local maxima (center of the islands in quadratic contour) and stationary response points. Once all the stationary response points have been identified, users can choose to rank the solutions by quality or can choose to use analysis of variance (ANOVA) methods to determine which main effects and/or interactions are of interest. Two separate layers were evaluated and compared to the process of reference (POR) brute force method of optimization. Results showed that the best residuals values from recipes optimized using 1-cycle SPOC-based automatic recipe optimization (ARO) and ARO based on the 2- cycle Brute-Force strategy were comparable to known residuals values from the POR recipes. Moreover, SPOC-based ARO was performed with a TTR of under 2 hours, while a 2-cycle Brute-Force ARO typically took 6~ 20 hours depending on specific configurations. The vast reduction in optimization time is primarily attributed to the elimination of multi-cycle refinement, whose data collection dominated the previously observed TTR. In conclusion, we demonstrated the ability to reduce time to solution by a factor of 3 while maintaining or improving on overlay residuals compared to existing brute force methodologies.
The semiconductor industry continues to push the limits of immersion lithography through multiple patterning techniques for printing features with critical dimension 20 nm and below. As a result overlay has become one of the critical lithography control parameters impacting device performance and has a stringent budget for yielding at smaller half pitch nodes. Overlay has several sources of errors related to scanner, lens, mask, and wafer. Lithographers have developed both linear and higher order field and wafer models to successfully compensate for the static fingerprints from different sources of error. After the static modeled portion of the fingerprint is removed, the remaining overlay error can be characterized as unstable modeled error or un-modeled error, commonly called uncorrectable residual error. This paper explores the fundamental relationship of overlay to wafer geometry through mechanisms of process-induced contributions to the wafer overlay, categorized as plastic and elastic wafer deformation. Correlation of overlay to local features such as slip lines is proven experimentally. The paper describes methodologies and geometry-induced overlay metrics for the application of wafer geometry to perform overlay feedback and feed forward applications. Feedback applications allow for process development and controlling semiconductor processes through in-line monitoring of wafers. Feed forward applications could include geometrybased corrections to the scanner for compensating non-static wafer geometry related overlay errors, and grouping wafers based on higher-order geometry.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.