Magnetic field effects in organic light emitting diodes have emerged as subject of intense research activities. We
investigated the recently discovered organic magnetoresistance effect, i. e. the phenomenon that the presence of
an external magnetic field can influence both the current flow through an organic light emitting diode and the
light emission from the device. Magnetoresistance measurements were performed in different device structures
as a function of magnetic field and driving voltage. We demonstrate that electrical conditioning can be used
as an efficient method to enhance the organic magnetoresistance effect in devices based on polymers and small
molecules. Depending on duration and intensity of the conditioning process the magnetoresistance effect can
be increased from ~1% to values exceeding 15% at 40mT in devices with poly(paraphenylene-vinylene) as
light emitting polymer. Qualitatively the increase in magnetoresistance can be correlated with a decrease in
luminance during the conditioning process. From this we conclude that degradation of the bulk emitter material
is responsible for the enhancement of organic magnetoresistance. In addition, we show a dependence of the
magnetoresistance effect on the charge carrier balance within the device. In bipolar devices the magnetoresistance
effect is significantly larger than in hole-dominated devices which suggests that electron-hole pairs play an
important role in the fundamental mechanism causing the organic magnetoresistance effect.
This paper discusses VLSI architectural support for motion estimation (ME) algorithms within the H.263 and MPEG-4 video coding standards under low power constraints. A high memory access bandwidth and a high number of memory modules is mainly responsible for high power consumption in various motion estimation architectures. Therefore the aim of the presented VLSI architecture was to gain high efficiency at low memory bandwidth requirements for the computationally demanding algorithms as well as the support of several motion estimation algorithmic features with less additional area overhead. The presented VLSI architecture supports besides full search ME with [-16, 15] and [-8, +7] pel search area, MPEG-4 ME for arbitrarily shaped objects, advanced prediction mode, 2:1 pel subsampling, 4:1 pel subsampling, 4:1 alternate pel subsampling, Three Step Search (TSS), preference of the zero-MV, R/D-optimized ME and half-pel ME. A special data-flow design is used within the proposed architecture which allows to perform up to 16 absolute difference calculations in parallel, while loading only up to 2 bytes in parallel from current block and search are memory per clock cycle each. This VLSI-architecture was implemented using a VHDL-synthesis approach and resulted into a size of 22.8 kgates (without RAM), 100 Mhz (min.) using a 0.25 micrometer commercial CMOS library.
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