Gravure printing is a very promising method for printed electronics because it combines high throughput with high resolution. Recently, printed lines with 2μm resolution have been demonstrated at printing speeds on the order of 1m/s. Here we build on these results to study how more complex patterns can be printed that will ultimately lead to printed circuits. We study how the drag-out effect leads to proximity effects in gravure when multiple lines are printed close to each other. Drag-out occurs as the doctor blade passes over the roll surface to remove excess ink from the land areas in between the cells that make up the pattern. In addition to this desirable removal of excess ink, some ink from the cells also wicks up the doctor blade and is removed from the cells. This ink is subsequently deposited on the land area behind the cells leading to characteristic drag-out tails. If multiple lines, oriented perpendicular to the print direction, are printed close to each other, the ink that has wicked up the doctor blade from the first line will affect the drag-out process for subsequent lines. Here we show how this effect can be used to enhance print quality of lines as well as how it can deteriorate print quality. Important variables that will determine the regime for printing optimization are ink viscosity, printing speed, cell size, cell spacing and relative placement of lines. Considering these factors carefully allows one to determine design rules for optimal printing results.
High-resolution features are key to achieve high performance printed electronics devices such as transistors. Gravure printing is very promising to achieve high resolution in combination with high printing speeds on the order of 1m/s. High-speed gravure has recently been shown to print high resolution features down to linewidths and spacing of 2μm. Whilst this was a tremendous improvement over previous reports, these results had been obtained using silicon printing plates. These silicon printing plates are fabricated using microfabrication techniques which offer several advantages over traditional metal gravure cylinders where the features are defined by techniques such as stylus engraving, laser engraving or etching. This offers much greater precision and design freedom in terms of feature size, surface roughness, cell placement and cell shape. However, rigid silicon printing plates cannot be used in a roll-to-roll printing process that would truly enable low-cost printed electronics. Here we demonstrate for the first time a gravure printing roll that combines the precision of silicon printing plates with the form factor of a metal cylinder. The fabrication process starts with a silicon master whose pattern is replicated by polymer molding. The actual metal printing plate is then built up on the polymer negative of the pattern by a combination of electroless and electroplating. After separation of the polymer and the metal, the metal printing plate can be mounted on a magnetic roll for printing. Printing of highly scaled 2μm features is demonstrated. Different metal surfaces were explored to optimize printing performance and wear during printing.
Printed electronics is attractive as a pathway towards the realization of ultra-low-cost RFID tags for replacement of conventional optical barcodes. While this application has received tremendous attention in recent years, it also represents one of the most challenging applications for organic transistors, based on both the performance requirements and the process complexity and cost implications. Here, we report on our progress in developing materials and processes for the realization of printed transistors for low-cost RFID applications. Using inkjet printing of novel conductors, dielectrics, and organic semiconductors, we have realized printed transistors with mobilities >0.1cm2/V-s, which is approaching the requirements of certain RFID applications. We review the performance of these devices, and discuss optimization strategies for achieving the ultimate performance goals requisite for realizing printed RFID.
Silicon-Germanium (SiGe) is a promising material for polycrystalline thin film transistors (TFTs) for active matrix liquid crystal display applications due to its low thermal budget and temperature requirements. The use of SiGe as the channel material in a TFT allows for faster crystallization and dopant activation at lower temperatures than possible with pure silicon. Thus, a SiGe-based TFT technology has great promise as a high-performance, high throughput, uniform, glass-compatible TFT process. Analysis of the SiGe system is difficult due to its binary nature. This complicates the development of optimization strategies for performance enhancement. The numerous variable sand interactions affecting the SiGe system make a standard factorial characterization impractical. In this paper, we present the results of a reduced multifactorial response surface characterization of the system. The results obtained have been used to define optimization strategies for improving device performance. Tests have shown the strategies to be valid over a wide range of conditions. Using these strategies, n- and p-channel TFTs have been fabricated using a glass-compatible process and they exhibit substantially better performance than previously achieved using a similar thermal budget process. Further optimization using the determined guidelines would enable the development of a manufacturable high-performance poly-SiGe TFT process. Phenomena affecting the SiGe deposition system have also been identified, suggesting bounds on the optimization windows.
Conference Committee Involvement (1)
Organic Field-Effect Transistors IV
31 July 2005 | San Diego, California, United States
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