KEYWORDS: Circuit switching, Capacitors, Analog to digital converters, Synthetic aperture radar, Design and modelling, Switches, Power consumption, Switching, Logic, Curium
The design of this paper is a 12bit SAR ADC,in order to optimize its performance and be able to achieve high accuracy, there are certain requirements for certain modules of the ADC. The design uses the bottom plate sampling, access to the common mode level Vcm on the upper pole plate of the DAC capacitor array is accessed by a higher precision bootstrap switch to reduce the non-linearity brought by the Vcm level access switch. By performing FFT simulation on the sampling points, it can be used at a sampling rate of 50Ms/s when the input signal frequency is 0.8301MHz and ENOB is 15.64bit. The capacitor array uses a combination of segmentation and splitting to greatly reduce the number of total capacitors, achieving only 188 unit capacitors, a 97.7% reduction in number compared to the conventional structure, for the entire ADC digital circuit The power consumption as well as the area of the ADC digital circuit has been significantly improved. The comparator uses a dynamic latching comparator to reduce power consumption while reducing the equivalent input noise of the comparator. The logic circuit uses dynamic SAR logic to control the analog-to-digital converter's successive comparisons. Sampling and analysis of the entire SAR ADC output achieves a valid bit count of 11.93 bits at a low frequency input signal of 0.1953MHz, enabling the conversion of a 12bit SAR ADC.
A new hybrid switching logical control circuit and an efficient capacitance DAC array is presented by combining split capacitor algorithm and common-mode switching algorithm in order to quickly establish the comparative logic of Successive Approximation Register Analog-to-Digital Converter(SAR ADC) during successive approximation. This circuit is a fully dynamic logic circuit that achieves high-speed conversion and is controlled by asynchronous timing in a different way. The split switching algorithm is adopted at the most significant bit (MSB) in the capacitive DAC array(CDAC), and the rest bits use the common-mode switching algorithm. This logic circuit can maintain the common mode level and reduces the switching power consumption as well. A 10bit SAR ADC is designed at the end. According to Spectre simulation, at a 1.8V supply and 25Ms/s, the ADC achieves an SNDR of 56.66 dB and the effective number of bit (ENOB) of 9.12bit, and the capacitance is reduced by 95.3% compared with the conventional method.
Electroencephalogram (EEG) signals are easy to be interfered by the artifacts of both electrooculogram (EOG) and electromyogram (EMG) during data acquisition. The two artifacts are unwanted in EEG signals processing but difficult to remove. In this paper, a novel blind source separation method for removal of both EOG and EMG based on the fast independent component analysis (FICA) and the independent vector analysis (IVA) is presented. The system uses both high-order statistics and second-order statistics to analyze the non-Gaussian and weak correlation of the artifact signals. Firstly, the FICA algorithm is used to decompose EEG into independent components. Next, the EOG artifacts will be identified and removed according to the window width of the separated EEG signals. Finally, an IVA Gauss-Laplace distribution (IVA-GLD) algorithm with an adaptive step size is exploited to remove the EMG artifacts. Experiments were carried out by the data set collected by a self-developed equipment. The root mean square error (RMSE) of the proposed method is 19.431, which is lower than the similar method without the peak window (23.118), and the correlation coefficient (CC) is 0.895, which is higher than the similar method without the peak window (0.799).
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