The thickness of the chalcogenide ovonic threshold switching (OTS) layer is one of the most critical parameters for the switch-only memory (SOM) process control. Traditionally, the OTS thickness and composition were measured by XRF using the amounts of Ge, As, and Se. Still, XRF has a few limitations in delivering the required performance, especially for products with multilayer memory architecture. For these products, x-ray fluorescence (XRF) signals overlap and cannot be used to measure the thickness of each layer. In the current paper, we have studied three new alternative approaches for measurements of the OTS thickness on-cell: Spectral Interferometry, Raman spectroscopy, and Hybrid Machine Learning technique. The first method, Spectral interferometry with the Vertical Traveling Scatterometry approach (VTS), allowed OCD modeling of the top of the structure by blocking the complex underlayers and measuring only the top OTS thickness on all targets, including within the chip. The second method, Raman spectroscopy, demonstrated oncell dimensional capabilities with an excellent correlation of the Ge-Se, As-Se, and Ge-Ge bonds of Raman active chalcogenide to TEM OTS thickness values. Finally, the third method used Raman parameters calibrated with TEM as a reference thickness for the ML solution using the VTS spectra on-cell. This ML method is fast, model-free, and requires minimal TEM samples for setup. All three methods have demonstrated capability for on-cell measurements and HVM process control.
In order to minimize wafer loss and increase productivity, it is important to predict the wafer yield drop caused by defects in early manufacturing stage. In conventional yield prediction method, the chip failure was manually checked using images sampled by defect inspection. However, it is insufficient to predict yield accurately since the prediction was performed with only a few sampled defect images. Furthermore, the kill-ratio per defect was not estimated properly because the electrical properties were not considered in predicting a failure such as short or open. In this paper, we propose a new yield prediction method using defect and layout information with the following two characteristics. We tried to overcome the existing sampling limitations by using the defect inspection raw data that contains the coordinates and size information of all defects. In addition, we matched the electrical signal information of the layout pattern with silicon directly and then calculated the kill ratio per defect. The kill ratio per defect has doubled from 30% to 70% applied to sub-20nm Emerging memory devices. And we have confirmed that the yield prediction gap, which is the difference between the predicted yield and the actual yield, decreases from 31% to 8%. It is expected to reduce wafer loss about 10% in Emerging memory devices and same improvement will occur in other products such as DRAM, FLASH, and LOGIC devices by applying this sophisticated methodology.
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