Dr. Youssef Drissi Profile

Dr. Youssef Drissi

at imec

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Publications (14)

Proceedings Article | 10 April 2024 Presentation + Paper

2D local interconnect metal patterning exploration for CFET

Hsinlan Chang, Youssef Drissi, Gioele Mirabelli, Odysseas Zografos, Yasser Sherazi, Julien Ryckaert, Gaspard Hiblot

Proceedings Volume 12953, 129530Y (2024) https://doi.org/10.1117/12.3010804

KEYWORDS: Extreme ultraviolet, Printing, Optical lithography, Extreme ultraviolet lithography, Metals, Transistors, Optical proximity correction, Deep ultraviolet

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Proceedings Article | 22 November 2023 Presentation

Application of SONR for a better OPC model with a EUV curvilinear photomask

Chih-I Wei, Rehab Ali, Andrew Burbine, Fan Jiang, Germain Fenger, Seulki Kang, Kotaro Maruyama, Yuichiro Yamazaki, Sujan Sarkar, Matteo Beggiato, Youssef Drissi, Werner Gillijns, Christophe Beral, Sandip Halder, Gian Lorusso, Philippe Leray

Proceedings Volume PC12751, PC127510Q (2023) https://doi.org/10.1117/12.2687822

KEYWORDS: Optical proximity correction, Photomasks, Extreme ultraviolet, Calibration, Semiconducting wafers, Scanning electron microscopy, Printing, Modeling, Machine learning, Data modeling

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Proceedings Article | 26 May 2022 Presentation + Paper

Design, patterning, and process integration overview for 2nm node

Syed Muhammad Yasser Sherazi, Yi-Han Chang, Youssef Drissi, Bilal Chehab, Jae Uk Lee, Victor Vega Gonzales, Ryan Ryoung Han Kim

Proceedings Volume 12052, 120520F (2022) https://doi.org/10.1117/12.2615311

KEYWORDS: Metals, Fin field effect transistors, Semiconducting wafers, Optical lithography, 3D imaging standards, Integrated circuits, CMOS devices, Standards development, Field effect transistors, Etching

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Proceedings Article | 5 March 2022 Presentation + Paper

Improving silicon-photonics inverse-design printability by leveraging SEM contours for advanced Optical Proximity Correction techniques

Youssef Drissi, Werner Gillijns, Sebastien Lardenois, Peter Verheyen, Guy Lepage, Mahmoud Mohsen, Maxence Delorme

Proceedings Volume 12012, 1201208 (2022) https://doi.org/10.1117/12.2609092

KEYWORDS: Optical proximity correction, Scanning electron microscopy, Semiconducting wafers, Silicon photonics, Photomasks, Metrology, Manufacturing, Silicon, Etching, Resolution enhancement technologies

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Proceedings Article | 22 February 2021 Presentation + Paper

EUV single patterning exploration for pitch 28 nm

Dongbo Xu, Werner Gillijns, Youssef Drissi, Ling Ee Tan, Apoorva Oak, Ryoung-han Kim

Proceedings Volume 11614, 116140Q (2021) https://doi.org/10.1117/12.2584730

KEYWORDS: Optical proximity correction, Semiconducting wafers, Metals, Extreme ultraviolet, SRAF, Lithography

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Proceedings Article | 26 September 2019 Presentation + Paper

A study of curvilinear routing in IN5 standard cells: challenges and opportunities (Poster Presentation)

Amit Dounde, Syed Muhammad Yasser Sherazi, Ryoung-Han Kim, Darko Trivkovic, Werner Gillijns, Youssef Drissi

Proceedings Volume 11148, 111481C (2019) https://doi.org/10.1117/12.2536899

KEYWORDS: Vestigial sideband modulation, Optical proximity correction, Standards development, Nanotechnology, Nanofabrication, Two photon polymerization, Adaptive optics, Electronic design automation, Metals, Mask making

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With the advent of Multi-beam mask writers, curvilinear shapes are being realized with comparable metrics to Manhattan shapes when it comes to write times which has been the main issue with conventional VSB mask writers. Techniques like PLDC also enhance Multibeam writing of complex curvilinear patterns. In the past Standard Cell (SDC) design was done with a gear ratio (polypitch/m1pitch) of 1:1. This inadvertently results in congestion on lower layers namely M1 as we try to push the design density. This can be improved by going to a gear ratio of 2/3 by which we derive additional M1 tracks (3 M1 tracks for every 2 poly) but the benefit derived out of a 2/3 gear ratio cell somewhat gets negated with the need for M2 in standard cells where MINT layer doesn’t fully cover M1. To resolve the problem with higher M2 usage in standard cells we can introduce 1.5D or curvilinear routing to make the final/minor routing connections. Here we try to present a study of different challenges and opportunities that arises as a result of introducing curvilinear routing in Standard cells (SDC). In IN5 technology node when we go for a gear ratio (CPP/M1Pitch) of 2/3 we observe that for every standard cell we will need two variants of the cell. These two variants have M1 which are interleaved and shifted. We can live with only one variant of the cell but this inadvertently leaves gaps in between standard cells as the M1 grids will not align when they are abutted. Further study of the impact of the need of two variants reveals that in some standard cells (~9% in IN5) we end up with using M2 for completing the connections. This has many drawbacks (extra routing resources, congestion on M2, increase in area and reduced performance) which negates the benefit derived with 2/3 gear ratio. To fix this problem we have two options. One is to use 1.5D routing and the other to use curvilinear routing. With this approach all the benefits of 2/3 gear ratio can be preserved (improved routing density, area and performance) without the need for M2. A design implementation of the same in IN5 AO22D2 standard cell with CPP of 45nm and M1 pitch of 30nm has been done and the M2 routing (with default approach) has been eliminated. Although this approach has numerous benefits and extended applications (in signal routing) it does present significant challenges when it comes to EDA tools, verification, mask and OPC. We are in the process of evaluating different test cases for design, mask and OPC challenges with curvilinear routing in IN5 SDC. On the design front the challenges include library characterization, PPA and runtime analysis, RC extraction and design verification. On the mask and OPC front some of the challenges include regular versus ILT OPC and their process window comparison, understand the SRAF’s required, mask data volume and MRC. A comprehensive understanding of the challenges and resolution of the same will entail a new scaling paradigm for standard cell designs and also enhance signal routing which in turn has numerous benefits when it comes to PPA.

Proceedings Article | 4 June 2019 Paper

Electrically measurable test structures to capture and classify EUV stochastics

Hemant Vats, Ryan Ryoung Han Kim, Yasser Sherazi, Youssef Drissi, Kurt Ronse

Proceedings Volume 10957, 109571M (2019) https://doi.org/10.1117/12.2515418

KEYWORDS: Transistors, Logic, Extreme ultraviolet, Stochastic processes, Metals, Printing, Bridges, Semiconducting wafers, Optical lithography, Lithography

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Proceedings Article | 21 March 2019 Paper

SALELE process from theory to fabrication

Youssef Drissi, Werner Gillijns, Jae Uk Lee, Ryan Ryoung han Kim , Ahmed Hamed-Fatehy, Rehab Kotb, Rajiv Naresh Sejpal, Germain Fenger, James Word

Proceedings Volume 10962, 109620V (2019) https://doi.org/10.1117/12.2517051

KEYWORDS: Manufacturing, Optical proximity correction, Extreme ultraviolet, Metals, Photomasks, Visualization, Scanning electron microscopy, Printing, Metrology, Optical lithography

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Proceedings Article | 21 March 2018 Presentation + Paper

Single exposure EUV of 32nm pitch logic structures: patterning performance on BF and DF masks

V. Blanco Carballo, J. Bekaert, J. H. Franke, R. H. Kim, E. Hendrickx, L. E. Tan, W. Gillijns, Y. Drissi, M. Mao, G. McIntyre, M. Dusa, M. Kupers, D. Rio, G. Schiffelers, E. De Poortere, J. Jia, S. Hsu, M. Demand, K. Nafus, S. Biesemans

Proceedings Volume 10583, 105830L (2018) https://doi.org/10.1117/12.2299639

KEYWORDS: Etching, Tin, SRAF, Optical lithography, Logic, Extreme ultraviolet, Photomasks, Stochastic processes, Scanning electron microscopy, Photoresist processing

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Proceedings Article | 16 October 2017 Presentation

EUV single patterning for logic metal layers: achievement and challenge (Conference Presentation)

Ryoung-Han Kim, Werner Gillijns, Youssef Drissi, Jae Uk Lee, Darko Trivkovic, Victor Blanco Carballo, Stephane Larivière, Rudi De Ruyter, Morin Dehan, Gregory McIntyre, Ling Ee Tan

Proceedings Volume 10450, 1045004 (2017) https://doi.org/10.1117/12.2281738

KEYWORDS: Photomasks, Extreme ultraviolet, Optical lithography, Logic, Optical proximity correction, SRAF, Data conversion, Metals, Manufacturing, Semiconducting wafers

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Proceedings Article | 26 April 2017 Presentation + Paper

Design and pitch scaling for affordable node transition and EUV insertion scenario

Ryoung-han Kim, Julien Ryckaert, Praveen Raghavan, Yasser Sherazi, Peter Debacker, Darko Trivkovic, Werner Gillijns, Ling Ee Tan, Youssef Drissi, Victor Blanco, Joost Bekaert, Ming Mao, Stephane Larivière, Greg McIntyre

Proceedings Volume 10148, 101480V (2017) https://doi.org/10.1117/12.2257885

KEYWORDS: Photomasks, Logic, Etching, SRAF, Extreme ultraviolet, Optical lithography, Metals, Computational lithography, Optical proximity correction, Semiconductor manufacturing

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Proceedings Article | 24 March 2017 Presentation + Paper

Reticle enhancement techniques toward iN7 metal2

W. Gillijns, L. E. Tan, Y. Drissi, V. Blanco, D. Trivkovic, R. H. Kim, E. Gallagher, G. McIntyre

Proceedings Volume 10143, 1014314 (2017) https://doi.org/10.1117/12.2258003

KEYWORDS: Metals, Extreme ultraviolet, Optical proximity correction, Extreme ultraviolet lithography, Reticles, Optical lithography, Calibration, Source mask optimization, Photomasks, SRAF, Semiconducting wafers

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Proceedings Article | 27 February 2015 Paper

Imec iSiPP25G silicon photonics: a robust CMOS-based photonics technology platform

Philippe Absil, Peter De Heyn, Hongtao Chen, Peter Verheyen, Guy Lepage, Marianna Pantouvaki, Jeroen De Coster, Amit Khanna, Youssef Drissi, Dries Van Thourhout, Joris Van Campenhout

Proceedings Volume 9367, 93670V (2015) https://doi.org/10.1117/12.2076262

KEYWORDS: Silicon, Silicon photonics, Semiconducting wafers, Waveguides, Germanium, Modulators, Photonics, Wave propagation, Standards development, CMOS technology

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Proceedings Article | 22 May 2013 Paper

ePIXfab: the silicon photonics platform

Amit Khanna, Youssef Drissi, Pieter Dumon, Roel Baets, Philippe Absil, J. Pozo, D. M. Lo Cascio, M. Fournier, J-M. Fédéli, L. Fulbert, L. Zimmermann, B. Tillack, T. Aalto, P. O'Brien, D. Deptuck, J. Xu, D. Gale

Proceedings Volume 8767, 87670H (2013) https://doi.org/10.1117/12.2020576

KEYWORDS: Silicon photonics, Computer aided design, Packaging, Photonics, Standards development, Device simulation, Prototyping, Microsystems, Semiconducting wafers, Etching

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Showing 5 of 14 publications

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