The talk will focus on back end short loop test chip design innovations jointly developed by Design Enablement and Process Technology Development teams at Intel. These short loop test chips serve as quick turn monitors and help to decouple frontend and backend process and yield development. The test chip design innovations, some using ML/AI techniques, allow fast sort testing for design rule coverage, product like layouts, known layout defect modes and litho hot spots. These test chips are designed with FA/FI features for fast debug and for driving process/yield development to low defect density (DD) regimes.

An overview of modeling of reactor and feature scale high aspect ratio (HAR) plasma etching will be provided, with emphasis on challenges raised by the recently released DOE Basic Research Needs (BRN) report "Plasma Science for Microelectronics Nanofabrication" for digital twins and integration with machine learning. Co-design principles will be discussed with examples taken from modeling of ONO-stack and DTI etching, and voltage-waveform-tailoring.

Transistor scaling has been one of the key engines driving Moore's Law and our semiconductor industry. To maintain this pace of scaling, many new architectural changes have been proposed, and introduced since the start of this century, such as FinFETs and gate-all-around (GAA). Many researchers agree that the next architecture change will go further in 3D by stacking transistors in what is called complementary FET or CFET. In this presentation, we will discuss benefits that CFET may provide, some CFET implementations as well as latest experimental demonstrations of CFET architectures. Specifically, we will highlight the opportunities and challenges in vertical patterning and aspect ratios required for what is referred to as self-aligned CFET. These include vertically stacked dual epi source-drain, vertically stacked dual metal gate workfunctions as well as backside interconnects. We will use recent progress in these technologies to experimentally demonstrate simple circuits in CFET architecture.

Sub 32-nm pitch line-space features with good within-wafer and local CD uniformity and tight line-end tip-tip spacing remains a challenge for EUV patterning technology. Maintaining line width and tip-tip spacing of exposed dimensions is a challenge for etch, leading to design limitations and increasing complexity for multiple modules. Applied Materials SculptaTM pattern shaping capability offers an alternative solution to these EUV patterning challenges. We report on several advances to this technology. (1) The ideal hardmask and etch material stack has been studied to improve tip-tip performance of 26-nm pitch line-space features with superior profile and CD control. (2) Using atomic layer deposition combined with Sculpta pattern shaping, a new technique has been demonstrated for EUV contact holes which can uniformly shrink CD in one direction and elongate in the other. This offers an attractive solution to improve uniformity of vias with sub 20nm CD, by starting from wider dimensions. (3) Sculpta pattern shaping technology has evolved to demonstrate a new capability for significantly improving rectangularity of line-end features and contact holes, in addition to unidirectio

The latest promising optoelectronic devices require complex 3D structures. In this study, optical grayscale microlenses and multi-height structures are etched into a polymer layer in a Capacitively Coupled Plasma reactor (CCP). Etching can cause profile deformation and surface roughness, which may affect device performances. A parametric study is conducted to investigate 3D etching mechanisms. We observed strong shape modulation by varying plasma parameters. Increasing chamber pressure, or decreasing High Frequency power, show similar tendencies, going from a rounded to a conic profile. Additional experiments suggest that 3D etching mechanisms rely on complex passivation processes and ion bombardment effects.

Mesa structures fabricated using a Plasma Etching process can introduce defects to the sidewalls & MQW region of a microLED display. Sidewall defects can increase the probability of non-radiative recombination losses especially in smaller pixel sizes. While ALE may be the emerging approach for uniform shallow low damage surface Etching, we can compare Mesa Sidewall conditions using both ALE and ICP principles Elevated etch electrode temperatures and/or radical dominated etches help, but the thermal budget has to be compatible with the upstream modules. Considerations of other contributors like mesa design or profile are also required. These decisions will impact the downstream integration, like dielectric conformality, generation of SiO2 voids during filling among others. This presentation will discuss uLED pixel output results relative to pixel size, shape & etching parameters. It will also show process integration challenges, how they were addressed and plans for future developments & improvements.

We present a universal surface kinetic model developed with a self-consistent numerical algorithm under a wide range of oxide etching process conditions. The deposition or etch yield can be calculated by considering both the passivation layer and mixed layers simultaneously. The proposed model was verified with experimental and atomic scale simulations. Finally, we integrated this model with 3D feature profile simulation to investigate the emerging issues in the plasma oxide process, such as low temperature and surface charging. The valuable knowledge from our integrated simulation will be discussed for the next-generation plasma oxide etch process.

In this paper, we introduce a method that employs a deep learning model, built with GPU, to extract contours from a variety of SEM images. The model is trained with images and their corresponding ground truth. Various models are explored, and their predictive results are juxtaposed with the known ground truth. In comparison with CPU, utilizing GPU can augment the speed approximately 20 times.

With transistor scaling entering Angstrom era, the ability to pattern small features using conventional lithography is increasingly challenging. One of the key limiters to such scaling challenges is commonly known as Edge Placement Error (EPE) which impacts the ability to successfully align layers to another without creating electrical shorts or opens. Area-selective deposition is one way to promote self-alignment and address edge placement challenges. The heart of this technique hinges on the ability to create a surface differential to overcome the inherent non-selectivity of deposition processes. This can be achieved by passivating the undesired areas exposed with organic blocking layers such as self-assembled monolayers (SAMs). A combination of such surface passivation techniques followed by Chemical Vapor Deposition (CVD) and Atomic Layer Deposition (ALD) processes can restrict thin film deposition on specific surfaces leading to area selective deposition. In this presentation, several critical challenges of ASD will be covered. The importance of defect identification and mitigation techniques will be discussed in the realm of various applications for area selective deposition.

Semiconductor processing has been advancing from the nano to the atomic scale. For atomic-scale processing, the plasma source need to be precisely controlled to minimize damage, such as UV radiation damage, ion-induced damage, and charge accumulation damage. In this presentation, we will introduce an Ultra Low Electron Temperature (ULET) plasma (Te < 0.5 eV) as a novel plasma source enabling us to perform damage-free plasma processing. We will also explain how to produce the ULET plasma. It is demonstrated that charge accumulation even in a patten with high aspect ratio is almost eliminated, and graphene remains undamaged in the ULET plasma, while it is heavily damaged in conventional plasma processes. The ULET plasma shows great promise for applications in atomic-scale plasma processing.

As IC device downscaling gets closer to the sub-10 nm critical dimensions, conventional deposition/litho/etch integration schemes and patterning processes, based on photolithography and etching, are facing their fundamental limits for device downscaling. Atomically controlled depositions at specific locations can boost advances or enable innovative fabrication schemes. Of several paths being explored for novel bottom-up nanopatterning, area-selective atomic layer deposition (ASD) and area-selective wet etch (ASE) are attracting increasing interest because of its ability to enable both continued dimensional scaling and accurate pattern placement for next-generation nanoelectronics. In this talk, an overview of potential applications of ASD and ASE in IC manufacturing is provided together with insights into the most relevant surface reaction mechanisms.

Semiconductor processing has been advancing from the nano to the atomic scale. For atomic-scale processing, the plasma source need to be precisely controlled to minimize damage, such as UV radiation damage, ion-induced damage, and charge accumulation damage. In this presentation, we will introduce an Ultra Low Electron Temperature (ULET) plasma (Te < 0.5 eV) as a novel plasma source enabling us to perform damage-free plasma processing. We will also explain how to produce the ULET plasma. It is demonstrated that charge accumulation even in a patten with high aspect ratio is almost eliminated, and graphene remains undamaged in the ULET plasma, while it is heavily damaged in conventional plasma processes. The ULET plasma shows great promise for applications in atomic-scale plasma processing.

Perfluorocompounds (PFCs) are widely used in various plasma etching processes are known as major greenhouse gases causing global warming. Replacing PFCs with gases having lower global warming potential (GWP) is considered as the ultimate solution. In this talk, the research on feasibility study of replacing PFCs with fluoroether and fluoroalcohol will be discussed for dielectric etching processes. Various fluoroethers and fluoroalcohols are pre-screened based on carbon/fluorine atomic ratio in molecules, molecular weight, boiling points, as well as global warming potentials, eight candidate gases were selected. Various chemical reactions were analyzed in plasma phase and on surface etching for the screened gases. Three different C4H3F7O isomers of fluoroethers and a fluorocalcohol were compared for both reactive ion etching reactions and plasma-based atomic layer etching processes. The emission characteristics of the processes were analyzed, and we demonstrated that the fluoroethers and fluoroalcohols can reduce global warming potential by more 80%.

Extreme ultraviolet (EUV) lithography offers finer patterning with a 13.5nm wavelength light source, surpassing ArF immersion lithography. However, EUV photoresist (PR) faces challenges such as low etch resistance and patterning issues due to high line edge roughness (LER). In this study, we investigated the effects of CS2 plasma treatment and subsequent annealing on the properties of EUV PR during CF4/Ar plasma etching. CS2 plasma treatment and CS2 plasma treatment followed by annealing improved the etch resistance of PR by reducing ΔLER, ΔCritical dimension, and ΔThickness compared to untreated or annealed PR. X-ray photoelectron spectroscopy and Fourier transform infrared spectroscopy revealed the formation of C-S and O=S bonds on CS2 plasma-treated EUV PR, contributing to these improvements.

Environmental sustainability is at the core of many recent studies, offering research opportunities to help meet the ambitious net-zero commitments defined by semiconductor companies. In this context, it is important to analyze the sustainability challenges that different process areas are facing. To enable process engineers to develop sustainable solutions, new metrics, suitable tools and clear targets need to be provided. In this paper we analyze how such tools should be crafted to help the definition of sustainable practices for semiconductors processing.

Direct print extreme ultraviolet (EUV) has proven effective for pitch scaling and design rules flexibility. As feature size shrinks, stochastic noise poses challenges that demand innovative solutions. In this abstract, we present a novel approach known as pattern shaping , that not only addresses these challenges but also facilitates new opportunities for advanced patterning strategies. Integrating pattern shaping applications into the process flow reduces process complexity, eliminates the need for additional EUV patterning layers, paves the way for pushing lithographic print boundaries, and enhances the wafer yield. This accelerates the achievement of the technology readiness milestones.

In this work, we demonstrate a self-aligned litho-etch litho-etch (SALELE) process flow for 18nm pitch patterning of subtractive Ru structures. This process combines many individual steps from a standard damascene double patterning flow with a spacer pull process to adapt it for subtractive patterning. Requiring two EUV exposures, this process flow enables a broad design space comparable to existing SALELE solutions for damascene integrations. Utilizing this process flow, we have demonstrated successful patterning of complex designs including intertwined comb-serpentines and various mixed pitch patterns. We report matched resistance for both mandrel and non-mandrel resistors. Additionally, we demonstrate equivalent yields for 1mm long intertwined comb-serpentine structures with serpentines formed from both mandrel and non-mandrel patterns.