A five-stage pipeline processor using the risc-v instruction set architecture designed by system verilog

Shuo Qi; Shao-peng Jin; Yi-hu Xu; Yi-lin Dai

doi:10.1117/12.2640295

23 May 2022 A five-stage pipeline processor using the risc-v instruction set architecture designed by system verilog

Shuo Qi, Shao-peng Jin, Yi-hu Xu, Yi-lin Dai

Proceedings Volume 12254, International Conference on Electronic Information Technology (EIT 2022); 122540M (2022) https://doi.org/10.1117/12.2640295
Event: International Conference on Electronic Information Technology (EIT 2022), 2022, Chengdu, China

Abstract

At present, the new instruction set architecture RISC-V has attracted the attention of many chip researchers. Research based on RSIC-V processor has also developed rapidly. However, many RSIC-V-based processor designs focus on short-stage pipelines such as two-stage pipelines or three-stage pipelines, and there are few classic five-stage pipeline designs. Based on this, a five-stage pipeline processor is designed using system verilog. In order to avoid the influence of the branch jump instruction on the execution efficiency of the processor, a prediction circuit based on the dynamic branch pre-method is added. And the data related controller is added to solve the data-related problem. Finally, Modelsim software is used to build a verification environment, and the basic instruction types of RISC-V such as logic operation instructions, arithmetic operation instructions and shift operation instructions are simulated and verified.

Citation Download Citation

Shuo Qi, Shao-peng Jin, Yi-hu Xu, and Yi-lin Dai "A five-stage pipeline processor using the risc-v instruction set architecture designed by system verilog", Proc. SPIE 12254, International Conference on Electronic Information Technology (EIT 2022), 122540M (23 May 2022); https://doi.org/10.1117/12.2640295

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