Prof. Yihu Xu Profile

Prof. Yihu Xu

at Yanbian Univ

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Publications (2)

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Proceedings Article | 13 June 2024 Paper

A study on hydroacoustic channel estimation based on improved OMP compressed perception algorithm

Zhiming Han, Hanbo Lu, Yihu Xu

Proceedings Volume 13180, 131803D (2024) https://doi.org/10.1117/12.3033751

KEYWORDS: Evolutionary algorithms, Neural networks, Signal processing, Wavelet transforms, Signal to noise ratio

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In this paper, for the OMP compressed perception algorithm, a channel estimation method in orthogonal frequency division multiplexing hydroacoustic communication system, a new compressed perception algorithm, BW-OMP (back propagation with wavelet - OMP), is proposed to be improved to realize the performance enhancement, and a new compressed perception algorithm, BW-OMP (back propagation with wavelet - OMP), is proposed, which utilizes the on-line learning of the BP neural network, and performs the neural network training in an iterative process, so as to give the better compensation of the channel estimation value, which is then used to compensate the channel estimation results of the original OMP compressed sensing algorithm. The compensation value is used to compensate the channel estimation result of the original OMP compressed sensing algorithm, so as to get the channel estimation result of the current moment with better performance. However, the complexity is increased, and in order to reduce the computational complexity, wavelet transform is introduced to decompose the reconstructed signal to achieve the purpose of improving the execution efficiency. Simulation results show that the proposed method has better channel estimation performance in terms of BER, channel estimation error and correlation compared with the traditional channel estimation algorithms (i.e., LS algorithm, MMSE algorithm, LMMSE algorithm, and the original OMP algorithm), and it is also demonstrated that the enhancement of the iterative process can help to improve the channel estimation performance of the OMP algorithm.

Proceedings Article | 23 May 2022 Paper

A five-stage pipeline processor using the risc-v instruction set architecture designed by system verilog

Shuo Qi, Shao-peng Jin, Yi-hu Xu, Yi-lin Dai

Proceedings Volume 12254, 122540M (2022) https://doi.org/10.1117/12.2640295

KEYWORDS: Logic, Signal generators, Computer arithmetic, Computer architecture

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At present, the new instruction set architecture RISC-V has attracted the attention of many chip researchers. Research based on RSIC-V processor has also developed rapidly. However, many RSIC-V-based processor designs focus on short-stage pipelines such as two-stage pipelines or three-stage pipelines, and there are few classic five-stage pipeline designs. Based on this, a five-stage pipeline processor is designed using system verilog. In order to avoid the influence of the branch jump instruction on the execution efficiency of the processor, a prediction circuit based on the dynamic branch pre-method is added. And the data related controller is added to solve the data-related problem. Finally, Modelsim software is used to build a verification environment, and the basic instruction types of RISC-V such as logic operation instructions, arithmetic operation instructions and shift operation instructions are simulated and verified.

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