The optical beamforming network (OBFN) is a promising alternative of traditional electronic phase shifter due to the advantage of eliminating the so-called beam squint behavior. Herein, a series of optical true time delay lines (OTTDLs) based on silicon on insulator (SOI) platform are proposed to produce OBFNs with multi-beam steering characteristics. A series of OBFN chips is designed to realize 34 specific delay steps between -21~+21 ps in order to achieve a nominal equal difference beam steering angle between ±45°. To pursue good beam quality, 32 delay waveguide channels are proposed according to the number of array elements. The optical carriers in each channel are densely multiplexed off-chip with a frequency difference of 100 GHz in C-band, and coupled on-chip by a grating coupler. Variable optical attenuators (VOAs) based on Mach-Zehnder interferometer (MZI) structure are introduced to tune the optical outputs of the 32 channels with a discrepancy less than ±1 dB. The OTTDLs are compatible with CMOS process, and appeared in a compact footprint of only 0.163 mm2 for a maximum true time delay of 651 ps. Such a compact waveguide layout leads to the footprint of a single chip within 2.5 mm×7.5 mm. Meanwhile, the operating temperature is under closed-loop control via a pair of thermoelectric cooler (TEC) and negative temperature coefficient thermistor (NTC). Together with hermetic package, the reliability of the OBFN chips can also be promoted.
Artificial neural networks have dramatically improved performance for many data processing tasks, including speech and image recognition. Today’s hardware based on von Neumann computering scheme is inefficient at implementing multiply-accumulate operations in neural networks. To tackle this issue, several kinds of electronic architectures have been developed, including GPU, FPGA and ASICs. However, with the gradual end of Moore's law, these architectures still encounter bottlenecks in terms of computation speed and power efficency. Recent years, optical computing technology has attracted much attention for its large bandwith and low latency, and significant effort has been made. Here we propose an integrated photonic chip that is capable of accelerating multiply-accumulate operations. The chip contains a cascaded array of 16 Mach–Zehnder interferometers which can be programmed to perform arbitrary 4×4 matrix. The theory simulation results of the device design are demonstrated.
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