Hybrid metrology solution for 1X-node technology

Alok Vaid; Alexander Elia; Mark Kelling; John Allgair; Carsten Hartig; Peter Ebersbach; Erin McLellan; Matthew Sendelbach; Nedal Saleh; Narender Rana; Hiroki Kawada; Toru Ikegami; Masahiko Ikeno; Takahiro Kawasaki; Cornel Bozdog; Helen Kim; Elad Arnon; Roy Koret; Igor Turovets

doi:10.1117/12.916940

4 April 2012 Hybrid metrology solution for 1X node technology

Alok Vaid, Alexander Elia, Mark Kelling, John Allgair, Carsten Hartig, Peter Ebersbach, Erin McLellan, Matthew Sendelbach, Nedal Saleh, Narender Rana, Hiroki Kawada, Toru Ikegami, Masahiko Ikeno, Takahiro Kawasaki, Cornel Bozdog, Helen Kim, Elad Arnon, Roy Koret, Igor Turovets

Author Affiliations +

Proceedings Volume 8324, Metrology, Inspection, and Process Control for Microlithography XXVI; 832404 (2012) https://doi.org/10.1117/12.916940
Event: SPIE Advanced Lithography, 2012, San Jose, California, United States

Abstract

The accelerated pace of the semiconductor industry in recent years is putting a strain on existing dimensional metrology equipments (such as CDSEM, AFM, Scatterometry) to keep up with ever-increasing metrology challenges. However, a revolution appears to be forming with the recent advent of Hybrid Metrology (HM) - a practice of combining measurements from multiple equipment types in order to enable or improve measurement performance. In this paper we extend our previous work on HM to measure advanced 1X node layers - EUV and Negative Tone Develop (NTD) resist as well as 3D etch structures such as FinFETs. We study the issue of data quality and matching between toolsets involved in hybridization, and propose a unique optimization methodology to overcome these effects. We demonstrate measurement improvement for these advanced structures using HM by verifying the data with reference tools (AFM, XSEM, TEM). We also study enhanced OCD models for litho structures by modeling Line-edge roughness (LER) and validate its impact on profile accuracy. Finally, we investigate hybrid calibration of CDSEM to measure in-die resist line height by Pattern Top Roughness (PTR) methodology.

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Alok Vaid, Alexander Elia, Mark Kelling, John Allgair, Carsten Hartig, Peter Ebersbach, Erin McLellan, Matthew Sendelbach, Nedal Saleh, Narender Rana, Hiroki Kawada, Toru Ikegami, Masahiko Ikeno, Takahiro Kawasaki, Cornel Bozdog, Helen Kim, Elad Arnon, Roy Koret, and Igor Turovets "Hybrid metrology solution for 1X node technology", Proc. SPIE 8324, Metrology, Inspection, and Process Control for Microlithography XXVI, 832404 (4 April 2012); https://doi.org/10.1117/12.916940

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