In this work we describe efforts to reduce the read noise in fully depleted, scientific charge-coupled devices (CCDs). The read noise is proportional to the total capacitance at the floating-diffusion node. Reductions in the capacitance at the floating diffusion are accomplished by implementing a direct contact between the output transistor, polysilicon-gate electrode and the floating diffusion. We have previously reported promising results for this technology that were measured on small-format CCDs with 4-channel readout where each channel had a different output transistor geometry. In this work we present the results of the use of this technology on 12 and 16-channel, large-format CCDs in order to determine the reproducibility of the process. The contact size for this work is two microns by two microns, and projection lithography was used to print the contacts. We have also utilized selective wafer-stepper lithography to generate contacts that are one micron on a side. We also describe efforts in the device design of the output transistor to further reduce the noise.
We describe work at Lawrence Berkeley National Laboratory (LBNL) to develop enhanced performance, fully
depleted, back-illuminated charge-coupled devices for astronomy and astrophysics. The CCDs are fabricated on
high-resistivity substrates and are typically 200–300 μm thick for improved near-infrared response. The primary
research and development areas include methods to reduce read noise, increase quantum efficiency and readout
speed, and the development of fabrication methods for the efficient production of CCDs for large focal planes.
In terms of noise reduction, we will describe technology developments with our industrial partner Teledyne
DALSA Semiconductor to develop a buried-contact technology for reduced floating-diffusion capacitance, as well
as efforts to develop ”skipper” CCDs with sub-electron noise utilizing non-destructive readout amplifiers allowing
for multiple sampling of the charge packets. Improvements in quantum efficiency in the near-infrared utilizing
ultra-high resistivity substrates that allow full depletion of 500 μm and thicker substrates will be described, as
well as studies to improve the blue and UV sensitivity by investigating the limits on the thickness of the back-side
ohmic contact layer used in the LBNL technology. Improvements in readout speed by increasing the number of
readout ports will be described, including work on high frame-rate CCDs for x-ray synchrotrons with as many as
192 amplifiers per CCD. Finally, we will describe improvements in fabrication methods, developed in the course
of producing over 100 science-grade 2k × 4k CCDs for the Dark Energy Survey Camera.
We describe the design and optimization of low-noise, single-stage output amplifiers for p-channel charge-coupled
devices (CCDs) used for scientific applications in astronomy and other fields. The CCDs are fabricated on highresistivity,
4000-5000 Ω-cm, n-type silicon substrates. Single-stage amplifiers with different output structure
designs and technologies have been characterized. The standard output amplifier is designed with an n+ polysilicon
gate that has a metal connection to the sense node. In an effort to lower the output amplifier readout
noise by minimizing the capacitance seen at the sense node, buried-contact technology has been investigated. In
this case, the output transistor has a p+ polysilicon gate that connects directly to the p+ sense node. Output
structures with buried-contact areas as small as 2 μm × 2 μm are characterized. In addition, the geometry of the
source-follower transistor was varied, and we report test results on the conversion gain and noise of the various
amplifier structures. By use of buried-contact technology, better amplifier geometry, optimization of the amplifier
biases and improvements in the test electronics design, we obtain a 45% reduction in noise, corresponding to
1.7 e- rms at 70 kpixels/sec.
A new-generation full-frame 36x48 mm2 48Mp CCD image sensor with vertical anti-blooming for professional digital
still camera applications is developed by means of the so-called building block concept. The 48Mp devices are formed
by stitching 1kx1k building blocks with 6.0 µm pixel pitch in 6x8 (hxv) format. This concept allows us to design four
large-area (48Mp) and sixty-two basic (1Mp) devices per 6" wafer. The basic image sensor is relatively small in order to
obtain data from many devices. Evaluation of the basic parameters such as the image pixel and on-chip amplifier
provides us statistical data using a limited number of wafers. Whereas the large-area devices are evaluated for aspects
typical to large-sensor operation and performance, such as the charge transport efficiency. Combined with the usability
of multi-layer reticles, the sensor development is cost effective for prototyping.
Optimisation of the sensor design and technology has resulted in a pixel charge capacity of 58 ke- and significantly
reduced readout noise (12 electrons at 25 MHz pixel rate, after CDS). Hence, a dynamic range of 73 dB is obtained.
Microlens and stack optimisation resulted in an excellent angular response that meets with the wide-angle photography
demands.
This paper presents an overview of the specific challenges that need to be overcome to make very-large CCD and CMOS
imagers, and presents some recent innovations in this area. The complete development chain is described: research,
production and industrialization. It will be shown that by innovative design and technology concepts, high-quality very large
area CCD and CMOS imagers can be made, even up to wafer size (6" for CCD, 8" for CMOS).
A 1/2 inch 1M-pixel monochrome Frame-Transfer CCD imager with 5.6μm by 5.6μm pixel size was developed for use in medical and industrial applications. The sensor production uses 17 mask steps designed for an improved process, with highly transparent membrane poly-silicon gates and two metal layers. The first metal layer is used for vertical strapping to reduce the RC- times of the imaging electrodes. The image pixels, the storage cells and the readout register are made using two layers of membrane poly-silicon. An n-channel implant on a profiled p-well in a n-substrate achieves 52,000 electrons full well charge storage capacity in combination with excellent vertical anti-blooming and fast electronic shuttering. Smear as low as 0.06% at 1/30 sec integration time is achieved at 5MHz frame shift frequency. The pixel charge is converted to an output voltage using a 3-stage source follower amplifier, optimized for 40MHz pixel frequency. For use in high-speed industrial applications, the split read-out allows pixel rates up to 80MHz. The output amplifier with a conversion gain of 18.7μV/electron has an rms noise of 18 electrons at full bandwidth (linear dynamic range of 67.8 dB). The dark current level is 100 pA/cm2 at 60° C.
To meet the continuous demand for more resolution in professional digital imaging, 22M pixels, 645-film format full-frame CCD image sensor was developed as an improved upgrade for an existing 11M pixel 35 mm CCD. This paper presents the device requirements, architecture, modes of operation, and evaluation results of the performance improvements.
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