We have developed a massive on-cell overlay metrology system based on Mueller matrix measurements. By integrating microscopic techniques into ellipsometry, we achieved high-throughput and extensive sampling coverage, with 1-shot/field per 1-field of view (FOV) measurement capability within a 34 x 34 mm2 FOV. Analyzing the off-diagonal components of the Mueller matrix allowed for on-cell overlay measurement across the wafer. This system provides measurement sensitivity comparable to e-beam-based technologies while offering high coverage, enabling precise reticle correction or high-order overlay correction in photolithography processes. This advancement represents a significant improvement in overlay metrology, offering both sensitivity and resolution for enhanced semiconductor manufacturing processes.
Depth profile of the dopant concentration in silicon substrate has a crucial influence on the electric characteristics that defines the device performance, whereas those profile has only been evaluated by destructive methods, most typically Secondary-Ion Mass Spectrometry (SIMS). We applied Terahertz Emission Spectroscopy (TES) that exploits charge carrier drift within the built-in potential structure to p-n junction structure in order to non-destructively extract the information about carrier dynamics and consequently the dopant profile. We prepared samples composed of Boron doped region as a p-Si and Phosphor doped region as a n-Si with a different p-n junction depth, and the TES evaluation was conducted illuminating the pump beam with the wavelength of 400nm. The obtained signals exhibit a clear difference among each sample in spite of the junction depth difference of as small as 15nm. The depth sensitivity of TES measurement was also investigated by utilizing carrier dynamics simulation, and clearly indicates the sensitivity to dopant depth profile, which is consistent with experimental TES signal. These results suggest that TES technology is very promising as in-line dopant profile measurement tool which is currently unrealistic with existing technologies and expected to greatly enhance the process control capability.
Scanning Electron Microscopy (SEM) technology makes use of an electron beam (e-beam) with wide energy range from 0.1 to 50 keV, so it is possible to measure wafers from surface to deep and buried structures. Due to its superior accuracy, it is widely used for in-line metrology and inspection (MI) process. As devices scaling down for performance enhancement, the MI process became inaccurate due to the target structure shrinkage and complicated electrons’ behavior inside it. To overcome the challenges, accurate simulation tool is required to understand its underlying mechanism theoretically. In this paper, we propose a unifying framework for simulating SEM operation by implementing Nebula e-beam computing algorithm on the Technology Computer-Aided Design (TCAD) environment. The proposed framework integrates various physics models including the scattering and transport behaviors of electrons, which enables to calculate the important trajectories of electrons in the most important regions of wafers. In addition, it gives an expandability on further integration thanks to the computability of TCAD environment. We validate the proposed framework with demonstrating key applications on real products.
We study the effects of annealing temperature on oxide charge trapping near the SiO2/Si interface using time-dependent second harmonic generation (TD-SHG), which is sensitive to charge separation near the interface. The TD-SHG signals are measured in plasma enhanced tetraethyl orthosilicate (PE TEOS) and high density plasma (HDP) oxide films deposited on silicon, respectively, which are typically used as intermetal dielectric (IMD) layers in 3D NAND. After annealing at temperatures ranging from 550 °C to 850 °C, the initial slopes of the TD-SHG signals at t=0, related to the charge trap density, decrease with increasing annealing temperature for PE TEOS, while the signals from HDP oxides show relatively flat curves independent of temperature even in the as-deposited state due to the reduced charge traps. The direction of the interfacial electric field resulting from the charge separation can be interpreted from the sign of the measured slopes. In PE-TEOS oxides annealed above 800 °C, the slope changes to the opposite sign, indicating the dominance of negative charges rather than positive charges. The observed TD-SHG results support previous suggestions that the electron trapping occurs in the carbon-related center of TEOS and appears to be dominant after high temperature annealing.
In recent years, the overlay specifications of advanced semiconductor devices have become extremely stringent. This challenging situation becomes severe for every new generation of the device development. However, conventional overlay metrology systems have limited throughput due to their point-based nature. Here, we first demonstrate the novel imaging Mueller-matrix spectroscopic ellipsometry (MMSE) technique, which can measure the overlay error of all cell blocks on a device wafer with extremely high throughput, much faster than conventional point-based spectroscopic ellipsometry (SE) technologies. It provides the super large field of view (FOV) ~ 20 × 20 mm2 together with high sensitivity based on Mueller information, which will be truly innovated solution not only for the overlay metrology, but also for critical dimension (CD) measurement, eventually maximizing process control and productivity of advanced node.
In this paper, we propose an unique metrology technique for the measurement of three-dimensional (3D) nanoscale structures of semiconductor devices, employing imaging-based massive Mueller-matrix spectroscopic ellipsometry (MMSE) with ultra-wide field of view (FOV) of 20×20 mm2. The proposed system enables rapid measurement of 10 million critical dimension (CD) values from all pixels in the image, while the conventional point-based metrology technique only measures a single CD value. We obtain Mueller matrix (MM) spectrum by manipulating wavelength and polarization states using a custom designed optical setup, and show that the proposed method characterizes complex 3D structures of the semiconductor device. We experimentally demonstrate CD measurement performance and consistency in the extremely large FOV, and suggest that the combination of MMSE and massive measurement capability can provide valuable insights: fingerprints originated from the manufacturing process, which are not easily obtained with conventional techniques.
An innovative metrology technique has been devised to address current limitations of optical critical dimension (OCD) in advanced semiconductor metrology. This technique is based on multiple self-interferometric pupil imaging, called Mueller matrix self-interferometric pupil ellipsometry (M-SIPE). The system integrates an innovatively designed interference generator in both illuminating and imaging optics, allowing for the massive acquisition of full polarization information across entire angles around the device. The vast amount of information can offer fully comprehensive structural analysis, accomplishing enhanced sensitivity and the ability to break the well-known parameter correlation issues. The system employs a single-shot holographic measurement technique on the pupil plane, enabling rapid acquisition of three-dimensional spectral information, such as wavelengths, incidence angles, and azimuth angles. Thus, unlike conventional OCD tools, M-SIPE can obtain multi-angular and full polarization information without any mechanical movements. We verified the performance of M-SIPE by the experiment of non-patterned wafers of various conditions using an optical testbed. Our results confirmed good agreement between the experiment and theoretical simulations across all angular ranges. Furthermore, the actual device simulation was conducted to show sensitivity enhancement and ability for breaking the parameter correlation issues. The results confirmed that the large amount of angular information from M-SIPE technique could overcome current metrological challenges.
High integration of semiconductor processes is being made to realize high performance in miniaturized chips. The performance of a semiconductor chip may vary depending on target variables such as thickness, line width, shape, composition, and physical properties of each layer constituting the chip. Therefore, in order to secure chip performance, accurate detection of target variable values and quality control are required, and it is necessary to check in advance for defects that may occur during the process. Optical inspection technology is widely used in the semiconductor metrology field due to its advantage in that it can detect defects in the wafer at high speed by scanning the wafer with a light source having a specific wavelength band. However, in recent years, the size of defects caused by high integration and miniaturization of semiconductor chip processes is getting smaller, and thus there is a limit to detecting micro defects using conventional optical methods. In this study, we propose an algorithm to improve the defect detection performance by utilizing multi-scan images acquired under various conditions. Using the suggested algorithm, it was confirmed that the SNR (Signal to noise ratio) of the defect of interest was improved by about 99%, and the classification performance for noise was improved by 4 times.
In case the process margin of the device is large and the defect tendency in the wafer occurs randomly, process monitoring were possible using limited sampling measurement values. Previous 3D structure metrology equipment (CD-SEM, ellipsometry, etc.) are not able to measure the entire structure of the wafer due to the speed limit. If the measurement location does not include a weak point, an error occurs in predicting the wafer defect rate. In this study, we propose a new method that can extract weak points from color maps obtained by high-speed inspection tools that can measure the entire wafer. We were able to reduce the process error by about 20% by weak point monitoring.
The era of big data and cloud computing services has driven the demand for higher capacity and more compact semiconductor devices. As a result, semiconductor devices are moving from 2-D to 3-D. Most notably, threedimensional (3D) NAND flash memory is the most successful 3D semiconductor device today. 3D NAND overcomes the spatial limitation of conventional planar NAND by stacking memory cells vertically. Since hundreds of vertically stacked semiconductor materials become the channel length in the final product, accurate thickness characterization is critical. In this paper, we propose a non-destructive multilayer thickness characterization method using optical measurements and machine learning. For a silicon oxide/nitride multilayer stack of <200 layers, we could predict the thickness of each layer with an average root-mean-square error (RMSE) of 1.6 Å . In addition, we could successfully classify normal and outlier devices using simulated data. We expect this method to be highly suitable for semiconductor fabrication processes.
In semiconductor industry, fast and effective measurement of pattern variation has been key challenge for assuring massproduct quality. Pattern measurement techniques such as conventional CD-SEMs or Optical CDs have been extensively used, but these techniques are increasingly limited in terms of measurement throughput and time spent in modeling. In this paper we propose time effective pattern monitoring method through the direct spectrum-based approach. In this technique, a wavelength band sensitive to a specific pattern change is selected from spectroscopic ellipsometry signal scattered by pattern to be measured, and the amplitude and phase variation in the wavelength band are analyzed as a measurement index of the pattern change. This pattern change measurement technique is applied to several process steps and verified its applicability. Due to its fast and simple analysis, the methods can be adapted to the massive process variation monitoring maximizing measurement throughput.
In this paper we proposed a new semiconductor quality monitoring methodology – Process Sensor Log Analysis (PSLA) – using process sensor data for the detection of wafer defectivity and quality monitoring. We developed exclusive key parameter selection algorithm and user friendly system which is able to handle large amount of big data very effectively. Several production wafers were selected and analyzed based on the risk analysis of process driven defects, for example alignment quality of process layers. Thickness of spin-coated material can be measured using PSLA without conventional metrology process. In addition, chip yield impact was verified by matching key parameter changes with electrical die sort (EDS) fail maps at the end of the production step. From this work, we were able to determine that process robustness and product yields could be improved by monitoring the key factors in the process big data.
In the era of sub-30nm devices, the size of the defects on semiconductor wafer has already exceeded the resolution limit
of optic microscope, but we still can't help using optical inspection tools. Therefore, the contrast enhancement technique
is more useful rather than the resolution itself. The best contrast can be taken by the optimized light conditions such as
wavelength, polarization, incidence angle and so on. However these kinds of parameters are not easily estimated
intuitively because they are strongly dependent on the pattern structures and materials. In this paper, we propose a
simulation methodology to find those optic conditions to detect sub 20nm defect. The simulation is based on FDTD
(Finite Difference Time Domain) calculation and Fourier optics.
The shrinking of design rule requires the short wavelength light used in the optical inspection system. However, the
existence of the condition that the long wavelength light becomes effective for the defect detection in line/space structure
is known. Calculation results using numerical simulation showed that the probe light can penetrate to the line/space
structure depending on the polarization even though the light has long wavelength. A new model was introduced to make
theoretical explanation of this abnormal behavior of long wavelength light and the mechanism of optical penetration was
clarified. In this model, the averaged extinction coefficient was calculated in consideration of the wavelength and the
period of the line/space structure. Using this model, the transmittance was calculated and compared with simulations.
The fact that the calculation result is agreed with the simulations showed this model's utility. This result shows that the
probe light can reach to the bottom of line/space structure in the inspection system for semiconductor devices even
though the light has long wavelength. It means that the long wavelength light can be used effectively for the defect
detection of the micro periodic structure in the semiconductor inspection system.
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