This PDF file contains the front matter associated with SPIE Proceedings Volume 11615, including the Title Page, Copyright Information, and Table of Contents.

Introduction to SPIE Advanced Lithography conference 11615: Advanced Etch Technology and Process Integration for Nanopatterning X.

The talk presents pertinent surface chemistries required to achieve a highly anisotropic etch of metal absorbers for EUV masks, with the goal of realizing a nearly vertical sidewall angle of 90º. The selection of gas phase chemistries is crucial to the success of the patterning process, therefore the selection criteria, based on thermodynamic and kinetic assessment, will be explained. The general approach combines either reactive ion etching or ion beam etching with atomic layer etching processes where the sequential surface reactions starts with controlled surface modification, followed by selective removal of the modified layer. This general approach can be applied to a variety of EUV mask materials, making it possible to tackle more complex material systems as needed.

Memory-hungry applications in the current data-driven economy demands DRAM devices with higher bit densities at a low cost. This demand has driven DRAM manufacturers to find innovative methods to extend Moore’s scaling and reduce the area required to store individual bits. A DRAM unit memory cell is based on a one transistor one capacitor (1T1C) design. To increase DRAM densities, both transistor and capacitor must scale. As the capacitor diameter shrinks with scaling, the ratio of its height to its diameter--its aspect ratio (AR)--climbs quickly. This higher AR results in the need to produce relatively deeper holes to fabricate capacitors, increasing the demands on etch and deposition processes. In this paper, we present a solution to capacitor scaling by co-optimization of the hardmask and etch. The co-optimization involved novel deposition and etch techniques to enable continued scaling while maintaining device performance. We also discuss novel metrology methods that enable us to test and optimize the unit processes as well as the module-level integrated sequence.

This paper describes how to overcome the challenges for EUV Lithography such as compatibility of performance, cost and defect reduction. The starting point application of innovative process technologies (e.g., high selectivity etching, atomic layer level control and so forth) to realize new booster technology in logic and memory. Post 5 nm co-optimization of novel film, etch and cleans technologies is critical to achieving cost effective process integration. However, fundamental advances in memory and logic still rely on dimensional controllability in high aspect patterns. A description of advances in these areas will round out the paper.

Extreme ultraviolet lithography (EUVL) has been adopted into high volume production for advanced logic device manufacturing. Due to the continuous size scaling requirement for interconnect fabrication, EUVL with self-aligned double patterning (SADP) formation has attracted substantial research attention [1]–[6]. Double patterning techniques in EUVL achieve pitch halving in the final feature by using the spacer defined approach and self-aligned block (SAB) mitigates the block placement error by leveraging etch selectivities and material filling capability. The current challenge in EUV SADP is the pattern transfer process from lithography to mandrel formation. In this step, the target critical dimension (CD) of the feature needs to shrink by half from the lithography CD during the etch process. The increasing aspect ratio during this etch potentially deteriorates the pattern validity and the line edge roughness (LER) [5]. In addition to these challenges, EUVL has a fundamental bottleneck due to stochastic effects which can lead to device degradation by defect formation and edge-placement-error (EPE) [7]–[10]. LER of the line and space pattern is one of the main contributors to EPE. Effective methods of LER reduction in both process and integration are needed in order to reduce pattern variation and boost device performance. In our research, we examine three approaches to reduce LER on the EUV SADP line pattern. This includes photoresist surface smoothing techniques, patterning layer material study, and tone inversion integration. The photoresist surface smoothing techniques involve a specific plasma process on the EUV chemical amplified resist (CAR) to achieve > 15% of improvement on LER from lithography to post etch performance. The patterning layer material study reveals an optimum patterning stack to minimize etch-induced line wiggling and etch selectivity requirements for LER performance. Finally, a first demonstration of EUV SADP tone inversion process integration is presented as a method to provide additional benefits to LER reduction. A detailed analysis of line performance from each processing step will be examined.

As EUV direct patterning begins to hit its resolution limit, the need for EUV self-aligned double patterning (SADP) has arisen in order to reach sub-30 nm pitch. Currently, EUV resists suffer from several shortcomings, both in terms of roughness and resist budget. These constraints means using it directly as a mandrel material, as previously done for immersion lithography SADP is nearly impossible. Consequently, standard EUV SADP flows involve the transfer of the resist through a lithography stack and into a hard mandrel material, such as silicon nitride or amorphous silicon.¹ Achieving line edge roughness (LER) and line width roughness (LWR) targets for an EUV SADP hard mandrel is significantly more challenging than for EUV direct print since the etch process needs to target a post etch CD of about half that of the lithographic CD. This aggressive shrink requirement usually involves degradation in roughness driven by high aspect ratios. To circumvent these issues, we have developed a new bottom up organic mandrel growth process, whereby the EUV resist can be grown to a height compatible with a resist mandrel SADP flow, while the roughness is improved and the critical dimension is controlled. This bottom up mandrel growth process is performed in an etch chamber and can therefore be easily coupled with other process steps. The mandrel height and critical dimensions can be easily tuned from the incoming lithography by changing the deposition and trim step times of the process. We have shown that this bottom-up grown mandrel can withstand typical ALD spacer process deposition. After spacer open, the organic material can be easily removed through an in-situ ash process before opening the underlayer. This integration will allow for the removal of the organic planarizing layer in the lithography stack, reducing the stack complexity, while also eliminating one of the major contributors to wiggling in the typical hard mandrel patterning scheme. In this paper, the performance of this new integration scheme was benchmarked against a more standard SADP flow. The roughness performance post mandrel formation and post spacer deposition for this new scheme is significantly improved over our standard EUV SADP baseline using a standard EUV SADP flow.

3D NAND flash scaling relies mainly on increasing vertical stack height, thus putting challenges mostly on film deposition and etch. Among various fabrication steps, high aspect ratio (HAR) ONON channel hole etch remains the most critical step. One unique aspect of the 3D NAND process flow is that nitride film in the ONON pair is a sacrificial layer that is been replaced with W at a later stage. The SiN removal process flow provides opportunities to look at possibilities of optimizing oxide and nitride films at different layers to enable better channel hole etch, such as enlarging bottom hole CD, reducing bowing and twisting in the middle area, and etc. In this paper, we will highlight the approaches and benefits on deposition and etch co-optimization as one potential pathway to overcome barrier in HAR ONON channel hole patterning. Besides ONON HAR, hard mask is another key focus. We will also discuss the possible mask material selection consideration based the overall film properties, etch selectivity and final clean/removability perspectives.

As contact dimensions continue to shrink to support scaling, local CD variation (LCDU) becomes a critical driver of electrical variation and defectivity. Continued logic scaling is highly dependent on middle of line (MOL), which further amplifies the need for LCDU improvement. LCDU improvement will be critical to improving edge placement error (EPE). The same concepts can also be applied to back end of line (BEOL) vias. Since lithography tools are unable to consistently print contacts below 20 nm, it is typically necessary to shrink through etch. There are various etch techniques we can use to shrink contact dimensions each having different impacts on LCDU and defectivity. In this study we explore the impacts of various shrink methods to optimize LCDU and defect density. In this study a simple patterning stack of SiN + OPL + ARC + resist is used to simulate contact patterning. Various etch chambers and shrink techniques are used to reach a target CD range and LCDU and defect density are evaluated. The chambers evaluated include TEL’s conductor etcher and TEL’s dielectric etcher. LCDU data is collected using CDSEM. Defect density is evaluated using various etch techniques. Etch techniques such as deposition on resist, ARC and OPL, descum steps, pulsing and quasi atomic layer etch are explored. Multiple types of deposition techniques are used including selective deposition and cyclic deposition and trim. These techniques are optimized to be sensitive to open area and correct for local CD variations. On wafer LCDU performance of <2.0nm is demonstrated and further optimization is done to minimize defectivity.

EUV lithography is moving forward to high volume manufacturing in DRAM production to overcome technological challenges in cell scaling. While EUV is confronting its own challenges, DRAM cell design rules have been scaled down using multiple patterning to extend the use of 193nm immersion lithography beyond its optical resolution limits . One of the big challenges in advanced DRAM nodes is to maintain the capacitance requirement while shrinking the capacitor size. By transitioning from square to honeycomb layout, the industry enabled taller capacitor s with larger diameters [1]. Those structures are patterned using spacer based pitch splitting techniques, but multi-patterning processes for capacitors need to ensure a high density arrays of holes are formed without losing critical dimension (CD) uniformity within the misalignment budget. In this work, we will demonstrate how to scale down capacitor pitch under 40nm using spacer based pitch splitting of lines and space to create honeycomb structures. Different strategies of self-aligned double patterning and quadruple patterning techniques to form a dense array of holes will be discussed. Furthermore, we will investigate how anti-spacer technique can play a role in local CD uniformity and placement in the final pattern.

3D and nanoscale dimensions make patterning extremely difficult to perform. In the past, patterning via plasma etching was a success thanks to the very good capacity of this process to etch one preferential material over the others: selective etching. Next step for advanced patterning will be to add a selective deposition step in addition to the etch one. Good examples are area selective deposition and topographical selective deposition. They will be discuss in this presentation

Self-aligned contact (SAC) etch has been known to be challenging due to its limited process margin on Si₃N₄ to SiO₂ etch selectivity. Understanding of surface modification during Quasi-ALE using fluorocarbon and Ar plasmas are essential to achieve atomic level control of etch pattern fidelity. In this paper, modeling techniques including first principal study, molecular dynamics simulation, chamber scale plasma simulation and Monte Carlo feature scale modeling have been incorporated to achieve physical demonstration of the Q-ALE process. Our study focuses on how the surface is modified by low energy ions followed by polymer accumulation by fluorocarbon neutrals at adsorption step under various plasma conditions to provide wide range of ion, radical densities with varied ion/radical ratios. Detailed surface evolvement including bonds, elements, structures, densities and depth information will be discussed with atomic level precision. In the Ar plasma desorption step, process dependence on ion energy angle distributions (IEADs) and ion fluxes has also been investigated. XPS surface analysis shows good agreement with modeling predictions. Modeling results and theories have reflected to process developments in next generation etchers with advanced pulsing, broad temperature control and other advanced features. Both blanket film etch rate and in-feature etch data will be discussed to validate the theoretical assumptions based on insights from modeling outputs. State of the art solutions with atomic level control and minimized nitride loss during SAC etch will be presented with in-depth fundamental understanding of correlations between innovative etch chamber designs and surface interactions.

The ability to etch silicon highly anistropically at active fin heights of 45nm or greater is critical to fin patterning for continued CMOS scaling. Tight control of fin CD and taper is critical toward controlling the device, with particular importance to channel control. In this study we explore the quasi-atomic layer etch (qALE) parameter space in order to better understand the impact of plasma conditions on fin CD, profile, and aspect ratio dependent etch phenomena. A qALE solution is needed to provide a manufacturable solution for a vertical square bottom fin. In this study a cyclic chlorination (surface modification) + ion bombardment process (modified surface removal) is used to etch Si with a Si3N4 hard mask. Various parameters are explored including bias power, pressure, and time in the ion bombardment step as well as source power, pressure, and time in the chlorination step. With regards to the ion bombardment step, varying time helps to quantify the self-limitation of the etch process, modulating pressure helps to quantify the impact of reduced mean free path and ion density, and modifying source power helps to quantify the impact of changes to ion density. For the chlorination step, varying time helps to quantify the self-limitation of surface modification mechanism, and modifying source power illustrates the impact of Cl radical density on surface modification. These various mechanisms will be explored with the particular view point of how these changes can impact ultimate channel performance.

Quantum computers perform calculations using quantum bits, or qubits, which can be made from superconducting circuits. These superconducting qubits allow direct control over device parameters while leveraging conventional Si-based fabrication techniques. MIT Lincoln Laboratory is designing and building high performance superconducting qubit devices with increased connectivity and addressability by utilizing advanced process techniques and 3D integration. Our three-tier stack architecture combines separately fabricated qubit, interposer, and routing chips with indium bump bonding. This stack contains high performance qubits, resonators, and couplers, superconducting air bridge crossovers, hard-stop spacing control, superconducting high aspect-ratio through-Si vias, and planarized superconducting routing layers. I will discuss our most recent accomplishments in the fabrication of three-tier stack devices and the effects of additional processing on the uniformity and integrity of their individual components.

Phase Change Memory (PCM) materials can be damaged during plasma exposure leading to changes in phase transition behavior. Etch-induced damage and crystallization properties of GeSbTe (GST) were evaluated as a function of substrate temperature, plasma chemistry, and plasma exposure time. Enhanced damage formation is related to selective elemental depletion and non-volatilized etch residue retention in the near surface region. These experiments validate literature findings that crystallization time increases with reduction in film thickness for GST samples capped with a thin SiO2 film, indicating the presence of a modified layer which serves as an interface layer material. A direct comparison of passivating properties of hydrofluorocarbon and hydrocarbon on GST can be more conclusive with a fine tuning of film thickness and an evaluation of total residue retention with depth profiling.

Slanted gratings show high efficiency in coupling light into waveguides, which is critical for optics such as the diffractive optical elements (DOEs) used in augmented reality glasses. Fabrication of master molds used for producing slanted gratings require high etch selectivity between SiO₂ and a metal mask. The industry standard for trench etch, Reactive Ion Etch (RIE), cannot produce slanted trenches. In this work, we demonstrate the fabrication of surface relief grating (SRG) master molds with slant angles of 30, 45 and 60 degrees. Using Reactive Ion Beam Etch (RIBE), etch anisotropy is controlled via the directionality of the ion beam, combined with angle of incidence. The selectivity between metal mask vs SiO₂ can be tuned (7:1 to 12:1). An in-house oxygen cleaning increases stability, leading to high repeatability in process and etch rates. High static uniformity across the wafer surface was achieved using a proprietary tunable ion source.

PPPL recently launched a new initiative in non-equilibrium plasma (NEP) science and technology with a focus on applications associated with key industries of the future (IotF), including semiconductor integrated circuit (IC) device manufacturing and materials associated with quantum information science (QIS). Multisector, cross-community partnerships with leading U.S. plasma semiconductor equipment suppliers and Princeton University have been started to support this initiative. The main challenge for NEP technologies in IC manufacture is atomistic control of chemical and material transformations at surfaces. This capability is also needed for future QIS device manufacturability, so fundamental research on NEP for future IC device manufacture is directly applicable to practical manufacturing of QIS devices. The big challenge for NEP is that it is chemically complex and often difficult to control. It took decades of research and development by plasma, surface, materials and device scientists and engineers to approach nm-scale precision processing with Si-based materials. The task of developing nm-scale processes for Si device manufacture is not complete, but next-generation IC manufacturing will also require significant changes in materials: i.e. 'post-Si materials.' The combination of new materials and increasingly, atomistic precision, challenges the current state-of-the-art in plasma technologies used for IC manufacture today. There are even bigger challenges for QIS materials and devices, especially when contemplating the need for developing devices with thousands or even millions of qubits. QIS devices can be made in multiple ways, but thin film approaches, based on existing IC manufacturing technology, have perhaps the best chance to manufacture at scale. Plasma technology is ubiquitous in QIS material fabrication involving thin film approaches, but plasma processes tend to create parasitic qubits and other serious atomic-scale defects. Solving these problems will require considerable research efforts - probably on a multi-decade timescale. In order to be successful, plasma scientists must work closely and collaboratively with specialists in surfaces, materials and devices. In this talk, I will outline the current and future plans for this new collaborative initiative at PPPL.

Analyses of unit process trace data are critical components of modern semiconductor manufacturing process control. While process development environments share many characteristics with manufacturing environments, development tools and processes may not be suitable candidates for the deployment of traditional trace analytics such as FDC applications. Here we describe the adaptive use of large scale, proactive process trace monitoring and reactive root cause analytics for supporting development operations. The large-scale monitoring application we have deployed is comprehensive in scope and scale and focusses on monitoring the stability of a chamber over time. The reactive root cause application we have deployed automatically searches large trace data spaces to identify trace data elements with potentially interesting relationships to variations in on-wafer measurements and is designed to handle the small sample sizes encountered frequently in development operations.

The research and development steps in the semiconductor industry require tools that are able to handle features with large variation across the images, but also tools that can reproduce the definition of an edge taught by an expert. This definition should be easily modified to mimic the expert decisions in order to reduce the time spent by process engineers during research and development phases. We developed a patterned edge model allowing to detect the profile of patterned objects in microscopic images. A complementary tool is proposed to customize the definition between two materials according to the expert targets. The obtained profiles serve as a basis to perform robust metrology and ensure quality control of the manufactured semiconductor components.

A method for automated creation and optimization of multistep etch recipes is presented. Here we demonstrate how an automated model-based process optimization approach can cut the cost and time of recipe creation by 75% or more as compared with traditional experimental design approaches. Underlying the success of the method are reduced-order physics-based models for simulating the process and performing subsequent analysis of the multi-dimensional parameter space. SandBox Studio™ AI is used to automate the model selection, model calibration and subsequent process optimization. The process engineer is only required to provide the incoming stack and experimental measurements for model calibration and updates. The method is applied to the optimization of a channel etch for 3D NAND devices. A reduced-order model that captures the physics and chemistry of the multistep reaction is automatically selected and calibrated. A mirror AI model is simultaneously and automatically created to enable nearly instantaneous predictions across the large process space. The AI model is much faster to evaluate and is used to make a Quilt™, a 2D projection of etch performance in the multidimensional process parameter space. A Quilt™ process map is then used to automatically determine the optimal process window to achieve the target CDs.

In this paper, we compare EPE (Edge Placement Error) variability among various multiple patterning techniques such as SADP and SALELE using simple restricted 2D design of “grating” (30 nm pitch) and “cut” (15 nm tip-to-tip) EUV patterns. The lithography variability contribution to CD uniformity is carried out through Tachyon® SMO generated contours by considering dose, focus, flare, mask variations. SEMulator3D is used to run a large Monte Carlo simulation to capture the following sources of variation: resist “contours” (from Tachyon®), spacer thickness, overlay for each of the lithography exposures and etch. We developed a methodology to combine lithography and other fab processes, particularly etch and deposition, involved in multi-patterning processes for EPE characterization of given layout. For the layout considered in this study, we find that Spacer Assisted Litho-Etch-Litho-Etch (SALELE) is more adaptable to multi-patterning process for extension to 2D layouts compared to Self Aligned Double Patterning (SADP). Per this study, the differences in the two multi-patterning approaches are primarily attributed to better litho performance (lower global CDU and larger process margin) and lower process variability on most process metrics.

Recently, the etch induced on-product overlay contribution as part of the total on-product overlay budget has received more attention. The main reason for this is that the etch induced overlay penalties are comparable to or even exceeding the state-of-the-art scanner overlay performance of approximately 1-nm. Large values from 4-nm to as much as 15-nm have been reported at the edge of the wafer. In order to mitigate these overlay penalties, solutions have been developed by both scanner and etch tool companies. Since the scanner has the capability to apply corrections per exposed field, the corrections can be optimized such that the overlay performance after etch is within the required specification. A potential drawback of this solution is that the underlying root cause is not taken away. A tilt in the etch direction that is causing the etch induced overlay penalty is compensated by a lateral offset by the scanner. A more elegant and preferred solution would be to optimize the etch tool hardware and/or etch recipe settings such that the etch direction is perpendicular to the wafer surface at every location on the wafer. To this end, dedicated hardware has been developed inside the etch chamber to compensate for the etch tilt in the etch direction at the wafer edge. Etch induced overlay effects were more recently also observed within each individual exposure field. A clear correlation with the pattern density distribution was found. Since these overlay penalties are static and repetitive from field to field, etch tool hardware changes are likely not the way forward to eliminate these kinds of overlay errors. For non-uniform pattern density distributions, a deep understanding of the details of the etch mechanism in combination with an optimized etch recipe is currently being considered to eliminate the intra-field etch induced overlay contributions. In earlier publications, the main focus was either on characterizing the etch impact on overlay or on understanding the impact of stressed layers on overlay. In this paper, we address the overlay impact after etching thin films that are deposited with either compressive or tensile stress. The deposition of the stressed films results in so-called umbrella- or bowl-shaped wafers. By varying the film thickness and composition, four different splits have been defined with warp levels of 40-μm and 80-μm for both shapes, respectively. First, the etch contribution for the different stressed layers is quantified. We will show that the etch induced overlay contribution does not depend on whether the stress in the deposited layer is compressive or tensile. This means that the etch induced overlay can be optimized independently of the properties of the stressed layer. Since the mask used has a non-uniform pattern density distribution, the stress distribution within the exposure field after the etching process will be non-uniform as well. This has a direct impact on the measured overlay after resist development for the subsequent litho layers. We will provide more clarity on the origin and nature of this overlay contributor. The goal of this paper is to characterize and better understand the overlay contributors associated with stressed layer etch. Additionally, we will provide solution directions to mitigate these overlay penalties.