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In the case of a homogeneous single film of uniform stress deposited on a substrate at elevated temperatures inside a deposition tool, the resulting free-form wafer shape at room temperature will take a parabolic form (either bowl or umbrella). The resulting in-plane distortion can be described by a radial scaling pattern. A linear wafer alignment model can easily correct for these kinds of distortion patterns and the resulting overlay is close to the scanner baseline performance. Also, in the case where there is a slight variation in one of the material parameters across the wafer, the resulting wafer distortion can easily be corrected for by selecting one of the available wafer alignment models. A Higher Order Wafer Alignment model up to the third order (HOWA3) has been proven to be sufficient to bring the overlay performance down to the scanner baseline performance over the past years.
In this paper we will consider the impact of local stress variations on the global wafer deformation. One of the sources of the local stress variation is linked to the intra-field or intra-die pattern density. We will demonstrate that the intra-field stress distribution not only affects the intra-field overlay performance but has also a significant impact on the global wafer distortion. The focus will be mainly on use-cases with high intra-field stress variations similar to what is encountered in 3D-NAND processes. These cases in particular need a more advanced correction approach. However, since the underlying root cause is generic, the same approach may also be applicable to other use-cases like DRAM and Logic.
In this work, we highlight one contributor that may negatively impact the on-product overlay performance, namely the etch step. The focus will be mainly on the wafer edge region but the remaining part of the wafer is considered as well. Three use-cases are examined: multiple Litho-Etch steps (LEn), contact hole layer etch, and the copper dual damascene etch. We characterize the etch contribution by considering the overlay measurement after resist development inspect (ADI) and after etch inspect (AEI). We show that the Yieldstar diffraction based overlay (μDBO) measurements can be utilized to characterize the etch contribution to the overlay budget. The effects of target asymmetry as well as overlay shifts are considered and compared with SEM measurements.
Based on the results above, we propose a control solution aiming to reduce or even eliminate the delta between ADI and AEI. By doing so, target/mark to device offsets due to etch might be avoided.
Test wafers were created by depositing a pattern transfer stack on a substrate representative of a 5 nm node target layer. The pattern transfer stack consisted of an atomically smooth adhesion layer and two hardmasks and was deposited using the Lam VECTOR PECVD product family. These layers were designed to mitigate hole roughness, absorb out-of-band radiation, and provide additional outlets for etch to improve LCDU and control hole CD. These wafers were then exposed through an ASML NXE3350B EUV scanner using a variety of advanced positive tone EUV CAR. They were finally etched to the target substrate using Lam Flex dielectric etch and Kiyo conductor etch systems. Metrology methodologies to assess dimensional metrics as well as chip performance and defectivity were investigated to enable repeatable patterning process development.
Illumination conditions in EUV lithography were optimized to improve normalized image log slope (NILS), which is expected to reduce shot noise related effects. It can be seen that the EUV imaging contrast improvement can further reduce post-develop LCDU from 4.1 nm to 3.9 nm and from 2.8 nm to 2.6 nm. In parallel, etch processes were developed to further reduce LCDU, to control CD, and to transfer these improvements into the final target substrate. We also demonstrate that increasing post-develop CD through dose adjustment can enhance the LCDU reduction from etch. Similar trends were also observed in different pitches down to 40 nm. The solutions demonstrated here are critical to the introduction of EUV lithography in high volume manufacturing. It can be seen that through a synergistic deposition, lithography, and etch optimization, LCDU at a 40 nm pitch can be improved to 1.6 nm (3-sigma) in a target oxide layer and to 1.4 nm (3-sigma) at the photoresist layer.
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