Advanced semiconductor devices target sub-2nm on-product overlay (OPO) and manufacturers utilize dense overlay (OVL) sampling and non-zero offset (NZO) control to enable such strict performance. Accurate optical OVL metrology systems with fast move-and-measurement (MAM) utilized at the after-develop inspection (ADI) step are required to support this OPO trend. This work presents an innovative Artificial Intelligence (AI) based, ultra-high-speed, overlay target focusing and centering approach on imaging-based overlay (IBO) measurements in the ADI step. The algorithm uses pre-trained image features and a deep learning model. The algorithm allows the measurement of every site across the wafer in its best centering and contrast focus position and thus overcomes intra-wafer process variations and enhanced measurement accuracy. The data will include results from multi-lot advanced DRAM process with basic performance analysis such as total measurement uncertainty (TMU), tool-to-tool matching (TTTM) and additional key performance indicators (KPIs).
The semiconductor industry continually evaluates new materials to improve the process or minimize product variability, which could create measurement challenges for metrology tools in the visible and near-infrared (NIR) spectrum. Opaque materials (i.e., ‘hard masks,’ ‘HM’) are placed in between the resist (i.e., inner layer) and process (i.e., outer layer or underlying layer) in 3D NAND or DRAM processes to control the etch of high aspect-ratio structures to maximize product yield. However, longer wavelengths (e.g., IR WL) may be required to penetrate and properly view the underlying process layer and measure OVL accurately. In this work, longer wavelengths will be evaluated to improve measurement accuracy and keep up with the increasing use of opaque materials, which is expected to increase in future nodes. We will review the benefits of IR WL to OVL measurement accuracy by quantifying the OVL residuals, contrast precision (CP), and total measurement uncertainty (TMU) on multiple DRAM and 3D NAND critical layers.
In modern DRAM processes, there are some critical layers that are particularly challenging for overlay (OVL) control. The conventional method of metrology target design for these challenging layers is to verify target performance using simulation based on the specific, final device process. After full simulations, target measurability issues can be encountered where the limited, available solutions (open hard mask, create topography, etc.) are costly and high risk. However, in DRAM new product R&D, there is always some tolerance for process tuning. The use of virtual Archer™ OVL measurements in metrology target design (MTD) can simulate metrology performance for these potential process splits, helping to find a good balance between process options and metrology performance. A significant improvement in target contrast for imaging-based overlay (IBO) is demonstrated by simulation on one of these challenging layers after process optimization as compared to the baseline (BSL) process. In this paper we will present the virtual MTD detailed flow and design considerations to achieve an optimized process and target design. The contrast of a key performance indicator (KPI) is improved by more than 30%, enabling OVL measurability of the challenging layer in new processes.
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