In this paper we will present initial results for logic and memory features imaged with the TWINSCAN EXE:5000 at the ASML-imec high NA lab after successful etch pattern transfer. For logic applications random logic metal designs (consisting of tight pitches and aggressive tip-to-tips) and corresponding via structures have been characterized for A14 and A10 nodes. As well, bidirectional designs enabled by high NA will be described. For memory applications, results from BLP/SNLP layer for D1d and D0a nodes will be presented.
KEYWORDS: Metals, Optical lithography, Fin field effect transistors, Extreme ultraviolet, Standards development, Silicon, Line edge roughness, Computer architecture, Process control
The targeted N3 technology node at IMEC is being redefined with respect to the poly pitch, as compared to the previous node definitions [1,2]. The overall industry trend of poly pitch scaling is slowing down, due to difficulties in keeping pace with device performance and yield issues. However, the metal pitch continues to scale down, which implies that direct pitch scaling will not lead to the most optimum scaling. Therefore, Standard Cell (SDC) track height reduction is a knob that can be used to achieve advances in the scaling of the technology to preserve Moore’s law. Here we present some of the options for the standard cell design that can enable an N3 technology node by using Design-Technology cooptimization (DTCO).
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