Dr. Soo-ryoung Lee Profile

Dr. Soo-ryoung Lee

Manager/CAE at Synopsys Korea Inc

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Publications (15)

Proceedings Article | 5 April 2011 Paper

Physical simulation for verification and OPC on full chip level

Seongbo Shim, Seongho Moon, Youngchang Kim, Seongwoon Choi, Younghee Kim, Bernd Küchler, Ulrich Klostermann, Munhoe Do, Sooryoung Lee

Proceedings Volume 7973, 79732I (2011) https://doi.org/10.1117/12.879577

KEYWORDS: Optical proximity correction, Lithography, Signal processing, Image quality, Nanoimprint lithography, Photomasks, Calibration, System on a chip, Data modeling, Computer simulations

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Proceedings Article | 23 March 2011 Paper

Improvement on post-OPC verification efficiency for contact/via coverage check by final CD biasing of metal lines and considering their location on the metal layout

Youngmi Kim, Jae-Young Choi, Kwangseon Choi, Jung-Hoe Choi, Sooryong Lee

Proceedings Volume 7973, 79732T (2011) https://doi.org/10.1117/12.870707

KEYWORDS: Etching, Metals, Optical proximity correction, Error analysis, Resolution enhancement technologies, Bridges, Photomasks, Model-based design, Head, Logic devices

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As IC design complexity keeps increasing, it is more and more difficult to ensure the pattern transfer after optical proximity correction (OPC) due to the continuous reduction of layout dimensions and lithographic limitation by k1 factor. To guarantee the imaging fidelity, resolution enhancement technologies (RET) such as off-axis illumination (OAI), different types of phase shift masks and OPC technique have been developed. In case of model-based OPC, to cross-confirm the contour image versus target layout, post-OPC verification solutions continuously keep developed - contour generation method and matching it to target structure, method for filtering and sorting the patterns to eliminate false errors and duplicate patterns. The way to detect only real errors by excluding false errors is the most important thing for accurate and fast verification process - to save not only reviewing time and engineer resource, but also whole wafer process time and so on. In general case of post-OPC verification for metal-contact/via coverage (CC) check, verification solution outputs huge of errors due to borderless design, so it is too difficult to review and correct all points of them. It should make OPC engineer to miss the real defect, and may it cause the delay time to market, at least. In this paper, we studied method for increasing efficiency of post-OPC verification, especially for the case of CC check. For metal layers, final CD after etch process shows various CD bias, which depends on distance with neighbor patterns, so it is more reasonable that consider final metal shape to confirm the contact/via coverage. Through the optimization of biasing rule for different pitches and shapes of metal lines, we could get more accurate and efficient verification results and decrease the time for review to find real errors. In this paper, the suggestion in order to increase efficiency of OPC verification process by using simple biasing rule to metal layout instead of etch model application is presented.

Proceedings Article | 23 March 2011 Paper

Fine calibration of physical resist models: the importance of Jones pupil, laser bandwidth, mask error and CD metrology for accurate modeling at advanced lithographic nodes

Seongho Moon, Seunghune Yang, Artem Shamsuarov, Eunju Kim, Junghoon Ser, Youngchang Kim, Seongwoon Choi, Changjin Kang, Ulrich Klostermann, Bernd Küchler, John Lewellen, Thomas Schmöller, Sooryong Lee

Proceedings Volume 7973, 79730X (2011) https://doi.org/10.1117/12.879592

KEYWORDS: Calibration, Photomasks, Scanning electron microscopy, Cadmium, Metrology, Data modeling, Critical dimension metrology, 3D modeling, Optical proximity correction, Laser metrology

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Proceedings Article | 29 September 2010 Paper

Integrated mask and optics simulations for mask corner rounding effect in OPC modeling

Jing Xue, Zhijie Deng, Kyoil Koo, James Shiely, Sooryong Lee, Yunqiang Zhang, Yongfa Fan, Thomas Schmoeller

Proceedings Volume 7823, 782341 (2010) https://doi.org/10.1117/12.866197

KEYWORDS: Photomasks, Optical proximity correction, Critical dimension metrology, Integrated optics, Calibration, Semiconducting wafers, Optical simulations, Process control, Control systems, Scanning electron microscopy

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Proceedings Article | 10 March 2010 Paper

A simplified reaction-diffusion system of chemically amplified resist process modeling for OPC

Yongfa Fan, Moon-Gyu Jeongb, Junghoon Ser, Sung-Woo Lee, Chunsuk Suh, Kyo-Il Koo, Sooryong Lee, Irene Su, Lena Zavyalova, Brad Falch, Jason Huang, Thomas Schmoeller

Proceedings Volume 7640, 764039 (2010) https://doi.org/10.1117/12.846737

KEYWORDS: Data modeling, Process modeling, Diffusion, Optical proximity correction, Semiconducting wafers, Calibration, Photoresist processing, Fiber optic illuminators, Chemically amplified resists, Molecules

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Proceedings Article | 4 March 2010 Paper

Improvement in process window aware OPC

Xiaohai Li, Yasushi Kojima, Hironobu Taoka, Akemi Moniwa, Matt St. John, Yang Ping, Randall Brown, Robert Lugg, Sooryong Lee

Proceedings Volume 7640, 76402O (2010) https://doi.org/10.1117/12.849904

KEYWORDS: Optical proximity correction, Lithography, Model-based design, Optical lithography, Process modeling, Roads, Lithographic illumination, Photomasks, Immersion lithography, Semiconductor manufacturing

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Proceedings Article | 11 May 2009 Paper

Double patterning addressing imaging challenges for near- and sub-k1=0.25 node layouts

Beom-Seok Seo, Dae-Kwon Kang, Myung-Soo Noh, Sung-Ho Lee, Christopher Cork, Gerald LukPat, Alexander Miloslavsky, Xiaohai Li, Kevin Lucas, Sooryong Lee

Proceedings Volume 7379, 73791N (2009) https://doi.org/10.1117/12.824300

KEYWORDS: Double patterning technology, Optical proximity correction, Silicon, Optical lithography, Photomasks, Logic, Etching, Manufacturing, Metals, Lithography

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A variety of innovations including the reduction of actinic wavelength, an increase in lens NA, an introduction of immersion process, and an aggressive OPC/RET technique have enabled device shrinkage down to the current 45nm node. The immaturity of EUV and high index immersion, have made logic manufacturers look at other ways of leveraging existing exposure technologies as they strive to develop process technology for 32nm and below. For design rules for sub-nodes from 32nm to 22nm, the need to define critical layers with double photolithography and etch process becomes increasingly evident. Double patterning can come in a variety of forms or 'flavors'. For 32/28nm node, the patterning of 2D features is so challenging that opposing line-ends can only be defined using an additional litho and etch step to cut them. For 22nm node, even line/space gratings are below the theoretical k1=0.25 imaging limit. Therefore pitch-doubling double patterning decomposition is absolutely required. Each double patterning technology has its own set of challenges. Most of all, an existing design often cannot be shrunk blindly and then successfully decomposed, so an additional set of restrictions is required to make layouts double patterning compliant. To decompose a logic layout into two masks, polygons often need to be cut so that they can be patterned using both masks. The electric performance of this cut circuitry may be highly dependent on the quality of layout decomposition, the circuit characteristics and its sensitivity to misalignment between the two patterning steps. We used representative logic layouts of metal level and realistic models to demonstrate the issues involved and attempt to define formal rules to help enable lineend splitting and pitch-doubling double patterning decomposition. This study used a variety of shrink approaches to existing legacy layouts to evaluate double patterning compliance and a careful set-up of parameters for the pitch splitting decomposition engine. The quality of the resultant imaging was tuned using double patterning aware OPC and printability verification tools.

Proceedings Article | 19 May 2008 Paper

AF fixer: new incremental OPC method for optimizing assist feature

Sung-Gon Jung, Sang-Wook Kim, Sung-Soo Suh, Young-Chang Kim, Suk-Joo Lee, Sung-Woon Choi, Woo-Sung Han, Joo-Tae Moon, Levi Barnes, Xiaohai Li, Robert Lugg, Sooryong Lee, Kyoil Koo, Munhoe Do, Frank Amoroso, Benjamin Painter

Proceedings Volume 7028, 70280Y (2008) https://doi.org/10.1117/12.793040

KEYWORDS: Atrial fibrillation, Optical proximity correction, Printing, Photomasks, Manufacturing, Scanners, Image segmentation, Process modeling, Optical lithography, Data modeling

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Proceedings Article | 19 May 2008 Paper

Mask process effect aware OPC modeling

Kyoil Koo, Sooryong Lee, Jason Hwang, Daniel Beale, Matt St. John, Robert Lugg, Seunghee Baek, Munhoe Do, Junghoe Choi, Youngchang Kim, Minjong Hong

Proceedings Volume 7028, 70283E (2008) https://doi.org/10.1117/12.793122

KEYWORDS: Photomasks, Etching, Optical proximity correction, Data modeling, Semiconducting wafers, Lithography, Statistical modeling, Wafer-level optics, Process modeling, Particles

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Proceedings Article | 12 March 2008 Paper

Optical proximity correction for elongated contact-hole printing

Young-Chang Kim, Sangwook Kim, Sungsoo Suh, Yongjin Cheon, Sukjoo Lee, Junghyeon Lee, Seong-Woon Choi, Woosung Han, Sooryong Lee, Kyoil Koo

Proceedings Volume 6924, 69243Q (2008) https://doi.org/10.1117/12.773819

KEYWORDS: Optical proximity correction, Photomasks, Diffusion, Printing, Critical dimension metrology, Instrument modeling, Statistical modeling, Optical lithography, Semiconducting wafers, Polymers

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Proceedings Article | 30 October 2007 Paper

Selective process aware OPC for memory device

Woosuk Shim, Sungsoo Suh, Frank Amoroso, Robert Lugg, Sooryung Lee, Sukjoo Lee, Seok-Hwan Oh, Junghyeon Lee, Tae-Hyuk Ahn, Chang-Jin Kang

Proceedings Volume 6730, 67302P (2007) https://doi.org/10.1117/12.747661

KEYWORDS: Optical proximity correction, SRAF, Photomasks, Data modeling, Semiconducting wafers, Lithography, Calibration, Process modeling, Printing, Inspection

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Proceedings Article | 29 May 2007 Paper

Stray-light implementation in optical proximity correction (OPC)

Young-Chang Kim, Donghyun Kim, Insung Kim, Sangwook Kim, Sungsoo Suh, Yong-Jin Chun, Sukjoo Lee, Junghyeon Lee, Chang-Jin Kang, Jootae Moon, Kunal Taravade, Sooryong Lee

Proceedings Volume 6607, 66071M (2007) https://doi.org/10.1117/12.728969

KEYWORDS: Optical proximity correction, Stereolithography, Stray light, Convolution, Photomasks, Modulation transfer functions, Spatial light modulators, Semiconducting wafers, Image quality, Critical dimension metrology

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Proceedings Article | 15 May 2007 Paper

Robust approach to determine the optimized illumination condition using process window analysis

Yong-Jin Chun, Sung-Woo Lee, Sooryong Lee, Young-Mi Lee, Sungsoo Suh, Suk-Joo Lee, Han-Ku Cho, Ho-Jin Park, Brad Falch

Proceedings Volume 6607, 660737 (2007) https://doi.org/10.1117/12.729026

KEYWORDS: Photomasks, Optical proximity correction, Nanoimprint lithography, Fiber optic illuminators, Image enhancement, Design for manufacturing, Critical dimension metrology, Semiconducting wafers, Lithography, Diffraction

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Several criteria are applied to optimize the best illumination and bias condition for a layer. Normalized image log-slope (NILS) and mask error enhancement factor (MEEF) are promising candidates to simply decide the optimized condition. NILS represents imaging capability and MEEF represents the mask uniformity influence on wafer image. MEEF has inversely relationship with NILS, but the optimized point of NILS does not exactly coincide with that of MEEF. Besides NILS and MEEF, the depth of focus (DoF) is an important factor for defining the process margin. The process window (PW) is expressed by DoF and exposure Latitude (EL). PW is general parameter used to determine the best lithographic condition. Large EL can be obtained at the condition with good image performance. In order to include mask uniformity effect in PW analysis, the common PW overlapping the final layout with positive and negative biased layouts is adopted. Starting with the minimum NA, sigma and threshold, OPC is performed to satisfy the target layout using aerial image model, and the final OPCed layout is obtained. The positive and negative biased layouts are generated from the final OPCed layout. The bias limit is determined considering mask uniformity. The common PW obtained by overlapping the final layout with positive and negative biased layouts is calculated. Then, NA, sigma and threshold are increased until the maximum values are reached. The common PW at each NA, sigma and threshold value is obtained using the same flow sequence. Comparing among calculated PWs, the NA, sigma and threshold of the maximum PW can be chosen as the best illuminator and bias condition. In this paper, the optimized illumination and bias condition is determined using PW for 60 nm memory device. The process flow is implemented by an OPC tool. By using the OPC tool for the illuminator optimization, the actual layout and multiple monitoring points can be measured. In spite of a large number of calculations, the fast calculation speed can be obtained by using the distributed process.

Proceedings Article | 26 March 2007 Paper

OPC in memory-device patterns using boundary layer model for 3-dimensional mask topographic effect

Young-Chang Kim, Insung Kim, JeongGeun Park, Sangwook Kim, Sungsoo Suh, Yongjin Cheon, Sukjoo Lee, Junghyeon Lee, Chang-Jin Kang, Jootae Moon, Jonathan Cobb, Sooryong Lee

Proceedings Volume 6520, 65200T (2007) https://doi.org/10.1117/12.711832

KEYWORDS: Optical proximity correction, 3D modeling, Photomasks, Near field, Polarization, Chromium, 3D image processing, Transmittance, Binary data, Optical lithography

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Proceedings Article | 20 October 2006 Paper

OPC to account for thick mask effect using simplified boundary layer model

Sangwook Kim, Young-Chang Kim, Sungsoo Suh, Sook Lee, Sungwoo Lee, Sukjoo Lee, Hanku Cho, Jootae Moon, Jonathan Cobb, Sooryong Lee

Proceedings Volume 6349, 63493I (2006) https://doi.org/10.1117/12.686394

KEYWORDS: Optical proximity correction, Near field, Polarization, 3D modeling, Photomasks, Critical dimension metrology, Chromium, Binary data, Optical lithography, Transmittance

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Showing 5 of 15 publications

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