The need for high-resolution metrology to verify lithography compliance with shrinking CD and overlay specifications has resulted in a variety of roadmap sanctioned approaches; notably, SEM, AFM and scatterometry. The application of optical microscopy has been relegated to overlay metrology. While high-resolution metrology is essential to the setup and qualification of lithographic processes, it is often ill suited to the demands of dynamic lithography control. The path to improved CD compliance is through improved on- produce dose and focus control. In control applications, enhanced sensitivity to what we are trying to control becomes a new handle on precision-to-tolerance. Sensitivity must be accompanied by ease of setup, speed and sampling. Modeling for correctable components of variation becomes an integral part of the metrology function. We show that the old dog optical microscopy can learn new tricks to encompass the control of dose and focus. In doing so it becomes the lead candidate for an integrated metrology solution.

We used two techniques to determine the sensitivity of a scanning-electron-microscope-based wafer-inspection system in detecting open-contact failures. (1) The correlation between the contact resistance and the brightness of the voltage-contrast image as captured by the system was obtained experimentally. (2) A voltage-contrast simulation was developed and applied to derive a correlation between resistance and brightness from these results. A close agreement between the experimental results and the calculated values was obtained. We succeeded in clarifying the determinants of the sensitivity of open-contact-failure detection. The brightness, over part of its range, appears to be proportional to log(R*I_p) where R is the resistance and I_p is the irradiating electron-beam current. This relationship indicates that the sensitivity of open-contact failure detection is determined by I_p. Control of I_p can be used to improve the voltage contrast, and this, in turn, can improve the sensitivity of detection.

In spite of the advantages of low cost and resistance, dual damascene process has some problems. When contact holes are patterned within the trench patterns, the contact holes are frequently found to be unopen and are bent toward trench side wall (TSW). These cause CD variation and small depth of focus. We can explain this phenomenon in view of limited resolution of photoresist (PR) and the light reflected from the TSW. The deeper the trench depth is, the thicker the thickness of the photoresist for contact hole patterns is, which leads to decreased resolution. And the light reflected off the TSW makes the contact hole's profile bent toward TSW. This reflected light influences on both sides. One is helpful in defining the contact holes near the TSW, and the other causes CD variations according to distance between the contact holes and TSW. If the contact holes and trench patterns are exactly the same sizes, it is possible to decrease the CD variation and to prevent PR contact holes from unopening within the trench patterns. Also it is of help to improve resolution at the bottom of the PR.

In the effort to extend the life of a technology node, reticle enhancement techniques are utilized extensively. The inspectability of advanced photomasks becomes increasingly difficult as OPC (Optical Proximity Correction) structures are incorporated in the mask design. OPC structures, such as serifs and sub-resolution assist features, are sub-specification (below the defined specification) geometries for the inspection tool. This makes it difficult to maintain high sensitivity on contamination inspection, while not detecting these OPC structures as false defects. Mask inspection can be broken down into two categories: pattern integrity and contamination, the latter of which is the topic of this paper.

Metrological data from sample surfaces can be obtained by using a variety of profilometry methods. Atomic Force Microscopy (AFM), which relies on contact inter-atomic forces to extract topographical images of a sample, is one such method that can be used on a wide range of surface types, with possible nanometer range resolution. However, AFM images are commonly distorted by convolution, which reduces metrological accuracy. This type of distortion is more significant when the sample surface contains high aspect ratio features such as lines, steps or sharp edges - structures commonly found in semiconductor devices and applications. Aiming at mitigating these distortions and recovering metrology soundness, we introduce a novel image deconvolution scheme based on the principle of stereo imaging. Multiple images of a sample, taken at different angles, allow for separation of convolution artifacts from true topographic data. As a result, perfect sample reconstruction and probe shape estimation can be achieved in certain cases. Additionally, shadow zones, which are areas of the sample that cannot be probed by the AFM, are greatly reduced. Most importantly, this technique does not require a priori probe characterization. It also reduces the need for slender or sharper probes, which, on one hand, induce less convolution distortion but, on the other hand, are more prone to wear and damage, thus decreasing overall system reliability.

Carbon nanotube tips offer a significant improvement over standard scanned probe microscope (SPM) tips for electrical characterization of nanodevice structures. Carbon nanotube tips are compatible with requirements for integrated SPM_probe station instruments in which SPM-based lithography, topography, electric force microscopy, and traditional current-voltage measurements are performed simultaneously or sequentially. As device dimensions shrink, traditional diagnostics will be unable to probe nanometer-scale phenomena that affect device performance and reliability. At the same time, the introduction of novel materials such as silicon-on-insulator into standard processing will require methods that can rapidly identify defects and their local behavior. Electric force microscopy with carbon nanotube tips offers unique capabilities for satisfying these needs.

A new automation software creates a search model as an initial setup and searches for a user-defined target in atomic force microscopes or stylus profilometers used in semiconductor manufacturing. The need for such automation has become critical in manufacturing lines. The new method starts with a survey map of a small area of a chip obtained from a chip-design database or an image of the area. The user interface requires a user to point to and define a precise location to be measured, and to select a macro function for an application such as line width or contact hole. The search algorithm automatically constructs a range of possible scan sequences within the survey, and provides increased speed and functionality compared to the methods used in instruments to date. Each sequence consists in a starting point relative to the target, a scan direction, and a scan length. The search algorithm stops when the location of a target is found and criteria for certainty in positioning is met. With today's capability in high speed processing and signal control, the tool can simultaneously scan and search for a target in a robotic and continuous manner. Examples are given that illustrate the key concepts.

This paper demonstrates the overlay capability of ASML's ATHENA alignment system on I-line steppers for W-CMP processes. The evaluation presents the method used to find the best scribe-line marks, alignment recipe and the long term overlay capability of ATHENA for a 0.35micrometers device in a production environment. This alignment capability for W-CMP meets the overlay requirement for the 0.35micrometers process and thus leads to device yield improvement.

This study assesses the effectiveness of applying zero and non-zero alignment strategies to backend layers of a 0.20 micrometers DRAM process using two alignment methodology (TTL, Through the Lens Alignment, and Athena, Advanced Technology using High-Order Enhancement of Alignment) to investigate alignment mark deformation resulting from a chemical- mechanical planarization (CMP) process and thus compensate the deformation-induced overlay errors. Additionally, a mathematical model is proposed to verify that the intra and inter registration errors in TTL alignment originates from non-zero mark deformation. Several parameters in the CMP process, including pad rotation direction and pad life time are also examined to reduce the deformation-induced overlay errors. Results in this study demonstrate the effectiveness of this approach for tight and correctable compensation within whole lots, thereby demonstrating the optimal combinations of the CMP process parameters, types of alignment marks, and corresponding alignment positions.

In this work, different overlay targets were evaluated for the Via first process with conventional USG dielectric. The etch stop layer nitride thickness was limited at 500 A as increasing this thickness will increase the RC delay which is undesirable. A series of targets were evaluated to find out the best performer. Target evaluation was done by their appearance, static repeatability, dynamic repeatability, target correlation, Tool induced shift, Overall misregistration, and residuals. Lot comparisons have also been done using selected targets. Lot average misregistrations (with the best target-2micrometers trench) of 9nm (X + 3(sigma) ), and 15nm (Y + 3(sigma) ) were obtained for the Metal 2 (M2) aligning to Via 1 (V1) level. The different Bar in Bar target structures evaluated were: a. Trench in trench : 1 micrometers and 2 micrometers trenches. b. Wall in wall : 1 micrometers Bars and 2 micrometers Bars. The trench in trench structures were found to work better than bar in bar for conventional dielectric Via first approach. The 2micrometers thick trenches gave the best results for target correlation, dynamic repeatability, and residual values. Metal 1 to metal 2 targets also gave good results and could be used. For low K dielectric and copper integration, a dual hard mask scheme was used. The dual hardmask was used to minimize the interaction of organic dielectric with organic barc and deep UV resist layer as this sometimes gives rise to poisoning issues. For the Organic Low K dielectric and Copper, where the dual hard Mask scheme was followed, the Wall in Wall target gave good contrast and the best results.

This paper demonstrates the impact of introducing air-shower unit over the stepper prealignment module on the overlay performance of 0.35micrometers process technology. There is a overall improvement in overlay by 8-12nm for the FEOL process (poly to active) and 25-30nm improvement for W-CMP BEOL process .

Advances in wafer processing techniques and the increase of wafer size to 300 mm present new challenges to overlay performance. This paper focuses on advances n the area of process-induced alignment accuracy using the ASML ATHENA alignment system. In the experiments, process variations were deliberately increased to characterize the influence of process-tool settings on wafer alignment performance. In the STI process flow, overlays of <32 nm on marks in silicon or marks in the STI layer have been achieved. In the back-end-of-line, aluminum layers exhibit a significant shift of alignment marks and off-line metrology targets. A geometrical model of the sputter tool is used to explain the origin of this effect. Possible improvements in process corrections are indicated. For the copper dual damascene process investigated here, the dielectrics are non-absorbing. Overlays of 25 nm on marks in silicon and 29 nm on marks in the metal layer are obtained. On 300 mm wafers, a new measurement method is capable of measuring process effects to an accuracy within 6.2 (3(sigma) ). This method is used to measure resist spin effects.

Overlay lot disposition algorithms in lithography occupy some of the highest leverage decision points in the microelectronic manufacturing process. In a typical large volume sub-0.18micrometers fab the lithography lot disposition decision is made about 500 times per day. Each decision will send a lot of wafers either to the next irreversible process step or back to rework in an attempt to improve unacceptable overlay performance. In the case of rework, the intention is that the reworked lot will represent better yield (and thus more value) than the original lot and that the enhanced lot value will exceed the cost of rework. Given that the estimated cost of reworking a critical-level lot is around 10,000 (based upon the opportunity cost of consuming time on a state-of-the-art DUV scanner), we are faced with the implication that the lithography lot disposition decision process impacts up to 5 million per day in decisions. That means that a 1% error rate in this decision process represents over 18 million per year lost in profit for a representative sit. Remarkably, despite this huge leverage, the lithography lot disposition decision algorithm usually receives minimal attention. In many cases, this lack of attention has resulted in the retention of sub-optimal algorithms from earlier process generations and a significant negative impact on the economic output of many high-volume manufacturing sites. An ideal lot- dispositioning algorithm would be an algorithm that results into the best economic decision being made every time - lots would only be reworked where the expected value (EV) of the reworked lot minus the expected value of the original lot exceeds the cost of the rework: EV(reworked lot)- EV(original lot)>COST(rework process) Calculating the above expected values in real-time has generally been deemed too complicated and maintenance-intensive to be practical for fab operations, so a simplified rule is typically used.

Traceable linewidth measurements of tiny features on photomasks and wafers present interesting challenges. Usually technical solutions exist for the problems encountered, but traceability can be costly in time and labor. A measurement is useful only if its value exceeds its cost. One such problem is that an optical or electron microscope forms a scaled image of the linewidth object, which is measured instead of the object itself. Interpreting this image to identify the object's edges in it can be difficult, because the image depends on instrument and object parameters (such as topography and materials) not directly related to the linewidth. Use of a linewidth standard can provide a traceable measurement if the relevant object parameters are known to match those of the standard. In the majority of cases, however, the object being measured and the linewidth standard will differ in topography and/or materials. Then the instrument images of object and standard will also differ, leading to possible measurement errors. Traceability requires that these measurement errors be quantified--a costly prospect. One can calculate the measurement error resulting from object/standard parameter differences. Then a measurement error tolerance can be chosen, and parameter tolerances can be found corresponding to a parametric measurement uncertainty that is consistent with it. These parameter tolerances define islands of tolerance in parameter space over which the parametric uncertainty will be tolerated. The larger the islands, the greater the measurement uncertainty, but the greater the number of different objects whose parameter differences fall on the island. While the calculations for the islands of tolerance may be complex, a single island can apply to a whole group of different objects, reducing the cost of measuring the parameters and calculating their effects. This is a way to obtain traceable linewidth measurements while balancing measurement cost and measurement uncertainty.

In a scanning electron microscope (SEM) top-down secondary electron image, areas within a few tens of nanometers of the line edges are characteristically brighter than the rest of the image. In general, the shape of the secondary electron signal within such edge regions depends upon the energy and spatial distribution of the electron beam and the sample composition, and it is sensitive to small variations in sample geometry. Assigning edge shape and position is done by finding a model sample that is calculated, on the basis of a mathematical model of the instrument-sample interaction, to produce an image equal to the one actually observed. Edge locations, and consequently line widths, are then assigned based upon this model sample. In previous years we have applied this strategy to lines with geometry constrained by preferential etching of single crystal silicon. With this study we test the procedure on polycrystalline silicon lines. Polycrystalline silicon lines fabricated according to usual industrial processes represent a commercially interesting albeit technically more challenging application of this method. With the sample geometry less constrained a priori, a larger set of possible sample geometries must be modeled and tested for a match to the observed line scan, and the possibility of encountering multiple acceptable matches is increased. For this study we have implemented a data analysis procedure that matches measured image line scans to a precomputed library of sample shapes and their corresponding line scans. Linewidth test patterns containing both isolated and dense lines separated form the underlying silicon substrate by a thin gate oxide have been fabricated. Line scans from test pattern images have been fitted to the library of modeled shapes.

Atomic force microscopes (AFMs) are used in the semiconductor industry for a variety of metrology purposes. Step height measurements at the nanometer level and roughness measurements at sub-nanometer levels are often of interest. To perform accurate measurements, the scales of an AFM must be calibrated. We have been exploring the use of silicon single atomic steps as height standards for AFMs in the sub-nanometer regime. We have also designed and developed the calibrated AFM (C-AFM) to calibrate standards for other AFMs. Previously, we measured the step height of silicon single atomic steps on Si (111) (with native oxide) using the C-AFM. The value we obtained was 304 +/- 8 pm (k=2). From three independent measurement techniques, including our C-AFM result, we estimate an accepted value for the silicon step height of 312 pm +/- 12 pm (k=2), which corresponds to an expanded uncertainty of about 4 %. We have also completed a NIST led comparison of AFM measurements of silicon step samples to further evaluate their suitability as standards in industrial applications. If the reproducibility of the participants' measurements is sufficient, the accepted value could be used to calibrate the scale of the measuring tools in this sub-nanometer regime. The participants sent the data to NIST for analysis. This was done so that all of the data would be analyzed in a uniform manner. The results of our analysis indicate that these samples can be used effectively as standards. The average standard deviation of all of the participants results was 6 pm. Hence, it should be possible to use these specimens as sub-nanometer z-axis calibration standards with an expanded uncertainty of about 6 %.

2D optical proximity correction is a requirement for feature patterning at 0.18 micrometers and below lithography process nodes. These corrections to semiconductor designs are intended to address the non-linearities of pattern transfer between mask making, lithography, and etch. Traditionally, IC patterns from design through etch have been characterized using critical dimension (CD) measurements. Semiconductor devices, however, are not simply made up of one-dimensional structures such as long lines and spaces. In many cases CD measurements alone are insufficient metrics of imaging performance. The fidelity of two-dimensional printed features is as important as the CD. This paper will examine the pattern fidelity of arbitrarily shaped two-dimensional patterns. Metrics such as pattern area, corner rounding, line end shorting, and the critical shape difference will be used as characterize the process. Both experimental and simulated data will be used to explore the importance of two-dimensional critical shape verses two-dimensional area on feature transfer.

The performance of an IC device, as we know, depends upon excellent linewidth control in lithography as the geometry of circuits is being decreased. The quality of the mask always plays an important role in this issue. As far as a wafer fab is concerned, the defective mask can lead to not only a dramatic drop in production yield, but also fatal damage for single-chip products. It is observed that a loss of transmission on a mask, detected by a reticle inspection system KLA303-UV STARlight (Simultaneous Transmitted And Reflected light) can bring about unacceptable CD variation on wafers. One major reason for the loss of transmission on masks is from the defect repair process, during which Gallium stain (Ga+) deposits onto the quartz on the chrome side of mask. This problem will become more and more critical for both mask houses and wafer fabs as long as the linewidth keeps shrinking and the design of denser pattern is inevitable. This purpose of this paper is to detail the correlation between wafer CD variation and the relative loss of transmission on the mask. By way of a designed test reticle processed with Gallium deposition by repair tool, inspection, exposure, CD data collection and analysis, we can clearly define the relationship based on I-line mask inspection light source. Following this work, the fab will be able to set up the inspection specifications for any incoming masks to prevent poor CD uniformity occurring in wafers. More importantly, with the design of a variety of patterns with different line/space ratios and device characteristics on this test reticle, we can try to predict the feasibility and severity of the transmission rate loss of mask for 0.15, 0.13 micrometers generations or beyond in order to help mask houses as well as wafer fabs get prepared and work out this problem prior to the advent of the next IC generation.

As dimensions get smaller and circuits get more complex, the demand for comprehensive measurements of reticule geometries increases. 3D characterization of phase shift mask (PSM) is required to understand the quality of the transferred image. To avoid anomalies between the measurements, the structures on both mask/reticule and wafer should be measured using the same technique. The technique used should be insensitive to differences in the intrinsic characteristics of the materials (chromium on quartz, resist on conductive or non-conductive layers). Scanning probe microscopy (SPM) is ideally suited to make these characterizations on both masks/reticule and wafers. It quantitatively profiles lines and trenches in three dimensions. SPM is a nondestructive technique, allowing for the preservation of the integrity of mask and wafers. The profiles of features on a phase shift mask (PSM) are measured with SPM. Some undesirable effects such as micro loading versus structure size during quartz etch, positive slope of the quartz sidewall, and CD differential between chromium and quartz are characterized. Some of the corresponding features on the wafer are measured with SPM and the correlation between the mask anomalies and their effect on wafer features are established.

One-dimensional linewidth alone is an inadequate metric for low-k1 lithography. Critical Dimension metrology and analysis have historically focused on 1-dimensional effects but with low-k1 lithography is has increasingly been found that the process window for acceptable imaging of the full 2D structure is more limited than the process window for CDs alone. The shape and area of the feature have become as critical to the proper patterning as the width. The measurement and analysis of Critical Shape Difference (CSD) of patterned features must be an integral part of process development efforts. Adoption of optical proximity correction (OPC) and other Optical Extension Technologies increases the need for understanding specific effects through the pattern transfer process. Sub-resolution features on the mask are intended to compensate the pattern so that the resulting etched features most accurately reflect the designer's intent and provide the optimum device performance. A method for quantifying the Critical Shape Difference between the designer's intent, OPC application, mask preparation, resist exposure and pattern etch has been developed. This work focuses on overlaying features from the various process stages and using CSD to quantify the regions of overlap in order to assess OPC performance. Specific examples will demonstrate the gap in current 1-D analysis techniques.

With the acceptance of etched phase shift photomasks by most major semiconductor manufacturers, it is necessary to build a significant number of these masks in a cost-effective and controlled manner. Optical methods of metrology used for many years in the photomask industry for binary masks are unsuitable for certain metrology applications related to etched phase shift photomask manufacture and repair. Atomic Force Metrology (AFM), Scanning Electron Microscope (SEM) metrology and optical methods, in combination, are now providing the necessary metrology tools to characterize etched phase shift masks and generate metrology for phase defect repair. Modeling methods such as electromagnetic modeling (EM) are providing insight into the effect of non- ideal processing on the final printed wafer image and the aerial image presented by a lithography system. This paper uses AFM metrology and EM modeling to explore the details of micro-trenching that occurs at the base of vertical walls on etched phase shift masks. Results of etch profiles obtained using AFM metrology are correlated with EM modeling of 320nm - 720nm etched structures in alternating aperture phase shift masks for use with KrF 4x reduction steppers. Three generically different etch processes were used to create the measured structures on six different masks. These six masks were manufactured by four different mask makers. The metrology and EM modeling results clearly differentiate each of the generic etch processes with the ICP + Iso etches showing 50% less micro-trenching relative to three of the four RIE-only etch processes. The simulation predicts the process window changes resulting from modeled micro-trenching relative to an ideal etch case. The models chosen for simulation represent the real etched results observed with the AFM. Comparisons of micro-trenching lengths measured during these experiments with the results of trenching bias across different etched space widths as reported by McCallum, et al. suggest that micro-trenching is a universal phenomenon occurring during quartz etches. It is proposed that micro- trenching more correctly defines the geometries responsible for trenching bias. Depth detail taken from the vicinity of an unusually shaped phase bump defect show the effect of local geometry on the extent to which trenching occurs. Trenching is more than 50% greater at the base of concave or acute defects as compared to convex defects. Further investigation of local trenching sheds light on the reason why phase bump defects near or touching a vertical trench wall appear more difficult to repair.

Optical overlay measurement methods are very effective since they are rapid and non-destructive. Imaging techniques need sophisticated image processing and suffer from the wave- optical resolution drawback. Presently, leading edge devices are offered with 5 though 10 nm measuring accuracy. In this paper a method is proposed that relies on the diffraction of a probing laser beam at a periodic reference pattern. This special pattern is implemented in the circuit layout. After the resist patterning of the second of two consecutive layers, the diffraction at the resulting net grating is measured. If an appropriate grating design is chosen, the misalignment error can be directly extracted from the diffraction efficiency. In order to obtain a strong diffraction signal and thus a sufficient signal-to- noise ratio optimum grating designs have been computed by means of rigorous diffraction modeling. Experimental results supported by rigorous modeling suggest that this technique could have the potential to meet next generation overlay accuracy requirements.

The continued downscaling of semiconductor fabrication ground rule has imposed increasingly tighter overlay tolerances, which becomes very challenging at the 100 nm lithographic node. Such tight tolerances will require very high performance in alignment. Past experiences indicate that good alignment depends largely on alignment signal quality, which, however, can be strongly affected by chip design and various fabrication processes. Under some extreme circumstances, they can even be reduced to the non- usable limit. Therefore, a systematic understanding of alignment marks and a method to predict alignment performance based on mark design are necessary. Motivated by this, we have performed a detailed study of bright field segmented alignment marks that are used in current state-of- the-art fabrication processes. We find that alignment marks at different lithographic levels can be organized into four basic categories: trench mark, metal mark, damascene mark, and combo mark. The basic principles of these four types of marks turn out to be so similar that they can be characterized within the theoretical framework of a simple model based on optical gratings. An analytic expression has been developed for such model and it has been tested using computer simulation with the rigorous time-domain finite- difference (TD-FD) algorithm TEMPEST. Consistent results have been obtained; indicating that mark signal can be significantly improved through the optimization of mark lateral dimensions, such as segment pitch and segment width. We have also compared simulation studies against experimental data for alignment marks at one typical lithographic level and a good agreement is found.

Overlay is one of the key designed rules for producing VLSI devices. In order to have a better resolution and alignment accuracy in lithography process, it is important to model the overlay errors and then to compensate them into tolerances. This study aimed to develop a new model that bridges the gap between the existing theoretical models and the data obtained in real settings and to discuss the overlay sampling strategies with empirical data in a wafer fab. In addition, we used simulation to examine the relations between the various factors and the caused overlay errors. This paper concluded with discussions on further research.

In this paper, we present an automated method for selecting optimal overlay sampling plans based on a systematic evaluation of the spatial variation components of overlay errors, overlay prediction errors, sampling confidence, and yield loss due to inadequate sampling. Generalized nested ANOVA and clustering analysis are used to quantify the major components of overlay variations in terms of stepper-related systematic variances, systematic variances of residuals, and random variances at the wafer, field and site levels. Analysis programs have been developed to automatically evaluate various sampling plans with different number of fields and layouts, and identify the optimum plan for effective excursion detection and stepper/scanner control. For each sample plan, the overlay prediction error relative to full wafer sample is calculated, and its sampling confidence is estimated using robust tests. The relative yield loss risk due to inadequate sampling is quantified, and compared with the cost of sampling in determining a cost-optimal sampling plan. The methodology is applied to overlay data of CMP processed wafers. The different spatial variation characteristics of oxide and metal CMP processes are compared and proper sampling strategies are recommended. The robustness of the recommended sample plans was validated over time. The sample plan optimization program successfully detected process change while maintaining accurate and robust stepper/scanner control.

SEM based CD control and wafer inspection has an increasingly active role in the semiconductor industry. Current design rules require a CD control with a precision in the nanometer range. In order to achieve this precision, a complete model of the image formation mechanism is desirable. For this reason we present a three-dimensional simulation of scanning electron microscope (SEM) images. The simulations include Monte Carlo electron scattering, charging in the substrate and electron ray-tracing in the column. We investigate some specific cases in CD-SEM metrology: We will describe the effect of scan orientation relative to the orientation of the imaged feature on the apparent beam width (ABW), the effect of magnification on contact imaging, and the effect of residue in resist trenches. Our results, regarding these examples, clearly indicate that a fully three-dimensional numerical simulation is needed to obtain an understanding of image formation and resolution limiting factors.

Charging effects on beam deflection of incident electrons in electron beam lithography are investigated. We show first in detail how the non-unity yield of electron generation in insulator resists leads to local charging accumulation and affects the beam deflection of incident electrons as charging develops. Then the amounts of beam deflection are identified for various operating and resist dimension conditions, and then we conclude that the beam deflection should be avoided for more accurate manufacturing semiconductor devices by the control of charging effects.

As the technology shrink to smaller Critical Dimension (CD) geometry, Spin On Glass (SOG) and Chemical Mechanical Polishing (CMP) techniques are employed. For 0.30/0.35micrometers processes that uses these techniques, wafer edge dies were having zero yield. These zero yielding wafer edge dies were found to be caused by topography difference between wafer edge and center due to coating, etching and polishing non-uniformity. The use of Wafer Edge Exposure (WEE) using ultraviolet light to create the Edge Bead Removal (EBR) on selected layers provide a more consistent and sharper EBR ring as compared to liquid EBR. This will also result in more complete dies at the wafer edge. The stepper is only able to provide either or no leveling information for the partial wafer edge fields due to the location of the field being too close to wafer edge. In this paper, we present an approach to resolve this problem which addresses the shortcomings of the stepper. We employ a manual top down CD Sem measurements on these non yielding wafer edge dies to check on the CD and profile, a different exposure and/or focus is/are than applied to these non yielding wafer edge field. KLA scan and sort yield are than used to confirm the effectiveness of the changes.

This paper demonstrates the use of lifted E2 nozzle with modified developer recipe in TEL MARK 8 track to reduce killer defects such as E2 nozzle imprints and contamination such as resist residues and developer strain. This concept has helped to improve machine uptime due to less occurrence of E2 nozzle related defects shutdown.

As modern circuit architecture features steadily decrease in size, more accurate tools are needed to meaningfully measure critical dimensions (CD). As a general rule, a metrology tool should be able to measure 1/10 of the product tolerance. As CD's continue to shrink, gauge control becomes more relevant. The trend is illustrated in Table 1. The standard in-line critical dimension measurement tool is the top-down scanning electron microscope (SEM). An emergine technology for high speed, high accuracy CD measurement is scatterometry. This paper will compare the two technologies for in-line CD measurement for three applications: A product etch step (assessing gauge capability as well as trending), a product resist step (trending), and lithographic cell monitors (trending).

Bake process of photo resist above glass transition temperature (Tg) increases its fluidity and shrinks contact holes patterned on the wafer. This process enables us to define sub-0.2 micrometers contact hole pattern with KrF, which is one of major issues of sub-0.15 micrometers device technology. However, the amount of PR flow depends on the contact hole size, pattern density and environment, which makes it difficult to control the fine critical dimension (CD) variation. In this paper, new approach to overcome the difficulties is studied with acetal type PR and attenuated phase shift mask (att. PSM). It is found that the change of chemical bonding in PR by light exposure decreases the resist flow sensitivity, which makes us solve the problems. The att. PSM enables us to control the aerial image intensity between contact holes, and the CD variation induced by bake process was drastically decreased when it is compared to Cr mask. The layout optimization by simulation for aerial image control in bulk region, and the resist flow process combined with att. PSM allows us to control the CD variation less than 20 nm for the sub-0.15 micrometers devices fabrication.

As the minimum feature size decreases down to 0.20micrometers , a minute pattern deformation can result in serious critical dimension variation. To minimize the critical dimension variation, the interaction of the positive-tone chemical amplification resist with SiOxNy type inorganic anti-reflective layer is investigated. The surface characterization of inorganic anti-reflective layer reveals that Si-NHx(x=0,1,2) and Si-N=O groups are attributed to the cause of the DUV PR footing. Based on the analyses, the technique to reduce the pattern deformation of the chemical amplification resist on inorganic anti-reflective layer is suggested.

Feed-forward, as a method to control the Lithography process for Critical Dimensions and Overlay, is well known in the semiconductors industry. However, the control provided by simple averaging feed-forward methodologies is not sufficient to support the complexity of a sub-0.18micrometers lithography process. Also, simple feed-forward techniques are not applicable for logics and ASIC production due to many different products, lithography chemistry combinations and the short memory of the averaging method. In the semiconductors industry, feed-forward control applications are generally called APC, Advanced Process Control applications. Today, there are as many APC methods as the number of engineers involved. To meet the stringent requirements of 0.18 micrometers production, we selected a method that is described in SPIE 3998-48 (March 2000) by Terrence Zavecz and Rene Blanquies from Yield Dynamics Inc. This method is called PPC, Predictive Process Control, and employs a methodology of collecting measurement results and the modeled bias attributes of expose tools, reticles and the incoming process in a signatures database. With PPC, before each lot exposure, the signatures of the lithography tool, the reticle and the incoming process are used to predict the setup of the lot process and the expected lot results. Benefits derived from such an implementation are very clear; there is no limitation of the number of products or lithography-chemistry combinations and the technique avoids the short memory of conventional APC techniques. ... and what's next? (Rob Morton, Philips assignee to International Sematech). The next part of the paper will try to answer this question. Observing that CMP and metal deposition significantly influence CD's and overlay results, and even Contact Etch can have a significant influence on Metal 5 overlay, we developed a more general PPC for lithography. Starting with the existing lithography PPC applications database, the authors extended the access of the analysis to include the external variables involved in CMP, deposition etc. We then applied yield analysis methods to identify the significant lithography-external process variables from the history of lots, subsequently adding the identified process variable to the signatures database and to the PPC calculations. With these improvements, the authors anticipate a 50% improvement of the process window. This improvement results in a significant reduction of rework and improved yield depending on process demands and equipment configuration. A statistical theory that explains the PPC is then presented. This theory can be used to simulate a general PPC application. In conclusion, the PPC concept is not lithography or semiconductors limited. In fact it is applicable for any production process that is signature biased (chemical industry, car industry, .). Requirements for the PPC are large data collection, a controllable process that is not too expensive to tune the process for every lot, and the ability to employ feedback calculations. PPC is a major change in the process management approach and therefor will first be employed where the need is high and the return on investment is very fast. The best industry to start with is the semiconductors and the most likely process area to start with is lithography.

Phase-shift masks are an important factor in the extension of optical lithography to the 50nmmode. A critical factor in their implementation is the "Dual reticle exposure technique." This technique uses two reticles: one is typically the high-resolution phase-shift reticle, and the other, a clearing or trimming reticle to remove unwanted phase edge patterns. This paper examines the result ofimplementing this technique on a very-high numerical aperture 193 nm-catadioptric-exposure system. Examples are given for the application of the "Dual Reticle Technique" including applications in which two phase-shift reticles are used to print advanced memory cells. Chromeless phase-shift masks are also shown. Issues with the implementation ofthe technique are examined. These include exposure delay effects, pattern registration, and the impact of the technique on exposure system throughput. Exposure system design developments are reported that will improve exposure system throughput with the dual reticle exposure technique. These include: Double Reticle Stages; and a new concept of exposing the two reticles simultaneously. It is noted that this dual simultaneous exposure system, when combined with a dual wafer stage system, has the potential for exposing 300mm wafers at rates up tp 150 wafers/hour in dual reticle exposure mode.

Achieving CD control for sub-100 nm processes will be challenging due to the low-k1 regime that optical patterning approaches will be required to work in. New challenges are expected to arise related to new lithography tools, photoresists, reticle types, and in some cases multiple exposures per layer. This work examines the intra-field CD variations for a range of sub-100 nm resist features patterned by chromeless phase-shift 248-nm lithography. One significant advantage of this patterning technique is that the resist CD's are a function of the exposure dose. This provides the ability to examine the CD variations of a range of linewidths in a single experiment without relying on reticle pattern scaling to determine the linewidth printed on the wafer. In addition to exploring CD control vs feature size, we also examine the full-field depth of focus for these features.

Astigmatism in the modem scanning electron microscope (SEM) is a leading cause oftool drift and poor precision. A straightforward and productive way of assessing astigmatism in an SEM involves determining the best focus settings for neighboring sets ofparallel edges ofdifferent orientations, typically: vertical, horizontal, and diagonal. Clearly if best focus is the same for all targets, then the working astigmatism ofthe instrument is zero. When these readings are unequal, the degree ofastigmatism is proportional to the deviation of individual readings from the mean. This then provides a quantitative way to monitor the degree of astigmatism. Alternatively, this provides the basis for a rapid algorithm for correcting astigmatism with a minimum ofbeam writing. This paper presents methods for objectively monitoring and correcting astigmatism in any SEM with automatic focus. This work also discusses the optimal choice of focus and linewidth measurement targets to use in automatic statistical process control practices for best sensitivity to astigmatism.

We use CD-SEM side-wall imaging using the Applied Materials VeraSEM 3d system as a destruction free and quick method to determine side-wall profiles. The system allows the reconstruction of profiles by tilting the SEM beam up to 6 degrees. Using two different tilt angles the reconstruction of side-wall profiles is possible in a quick and destruction free way even for negatively sloped profiles. The use of the profile analysis utility is believed to reduce cycle time significantly especially for process development and troubleshooting in production. We compare profiles obtained from the profile analysis utility of the VeraSEM 3D to X-SEM measurements to qualify this method for use in development and high volume production. For selected examples containing resist lines we investigate process windows determined from topdown CD measurements, X-SEM measurements and the profile analysis utility and compare the best stepper focus and exposure dose values obtained from these methods. It is shown how the results from the profile analysis utility can be used for process monitoring by comparing the obtained data to reference data from FEM wafers.

Automated critical dimension (CD) metrology has long been known to have certain limitations. As a top down imaging technique, retrograde profiles, resist thickness loss and other process issues are difficult to detect with the standard production CD SEMs used throughout the industry. Tilting capability has recently added much needed degrees of freedom to CD SEMs, potentially opening the door to three dimensional metrology. Various methodologies can be used to interpret tilt image information. This paper investigates one particular technique used to extract three dimensional information. Using cross section and/or atomic force microscopy (AFM), one can evaluate the potential benefits and validity of CD SEM tilt capability. Sidewall angle, film thickness and possibly other parameters could possibly become standard calculations the top down CD SEM could perform on a routine basis. Data is reported comparing 3D information generated from top down CD SEM to AFM. Potentially, a couple of different approaches to evaluating 3D information will be compared. Lastly, recommendations for future applications will be discussed.

A variety of techniques to characterize the lithographic quality of top-down two-dimensional patterns are described. Beginning with a top-down SEM micrograph, image processing and feature edge detection are used to extract a polygon representation of the printed pattern. Analysis on the polygon yields metrics such as corner rounding radius, feature area, and line edge roughness. Comparison of two shapes (for example, actual compared to desired, mask compared to wafer, or before etch compared to after etch) produces metrics such as overlapping area and the critical shape difference. Numerous examples of the utility of this approach will be given for SEM images of masks and wafers. The result is a set of numeric metrics of two-dimensional pattern fidelity applicable to lithographic evaluation, improvement and control.

A promising use for image and waveform correlation measurements now possible on modern CDSEMs is to monitor pattern fidelity in printing for multiple structural dimensions. This work explores some ofthese possibilities specifically for image correlation. Two different CDSEM-based pattern recognition engines and off-line image correlation with several image enhancement techniques are examined. The printing fidelity of an unassisted cross as a function of stepper focus and dose is studied because the variations of the structural details demonstrate many of the issues of concern in lithography today. Strategies for extracting the most information with the least beam writing are also explored. In some examples the pattern recognition score is directly interpretable in terms ofprinting fidelity. With additional calibration overhead associated with a particular lithography process, scores can be interpreted in terms ofprinting variables such as defocus and dose. The conflict in goals for using image correlation for navigation versus monitoring pattern fidelity is also discussed.

Conventional scanning electron microscopes are now close to the limit of their performance for tasks such as the metrology of sub-micron design rule devices. In order to overcome these limits we are investigating the use of in-line electron holography for device metrology. The in-line holograms are formed in a point projection microscope using ultra-low energy electrons (50-250eV) emitted from a nano-tip electron source. Holograms in the transmission mode and in the reflection mode of the microscope as well are possible. Since these in-line holograms are equivalent to out of focus micrographs acquired in a transmission electron microscope with a field emission gun we can reconstruct the original wave front by means of Fourier optics. The resolution of the point projection microscope is given by the sharpness of the emitter. We investigate the electric potential of the emitter using off-axis electron holography in a transmission electron microscope and compare the results to simulations obtained by solving the appropriate Laplace equation.

The development of EUV lithography, has made high-accuracy at-wavelength metrology necessary. Radiometry using synchrotron radiation has been performed by the German national metrology institute, the Physikalisch-Technische Bundesanstalt (PTB), for almost 20 years. Recently, PTB has set up four new beamlines for EUV metrology at the electron storage ring BESSY II. At a bending magnet, a monochromator for soft X-ray radiometry is routinely used for reflectometry and detector characterisation. A reflectometer designed for mirrors up to 550 mm in diameter and 50 kg in mass will be operational in January 2002. Detector characterisation is based on a primary detector standard, a cryogenic electrical substitution radiometer. Measuring tools for EUV source characterisation are calibrated on this basis. Detector testing at irradiation levels comparable to the anticipated conditions in EUV tools is feasible at a plane grating monochromator, installed at an undulator optimised for EUV radiation. A test beamline for EUV optics alignment and system metrology has been installed, using undispersed undulator radiation. Bending magnet radiation is available at a station for irradiation testing. A focusing mirror collects a radiant power of about 10 mW within the multilayer bandwidth and a 1 mm² focal spot.

We demonstrate the application of small angle neutron scattering (SANS) measurements for the quick, nondestructive, and quantitative measurement of the feature shape and size and line-edge roughness of lithographically prepared structures using a model photoresist pattern consisting of a periodic grating of 0.15micrometers lines. The measurements are performed directly on structures as fabricated on a silicon wafer with no other sample preparation. For well-defined patterns placed normal to the neutron beam, we easily observe up to six orders of diffraction peaks. Analytic expressions from standard small angle scattering formalism are sued to extract the average line structure, spacing, and line-edge roughness from the peak positions and intensities. Additional structural information is obtained by tilting the pattern relative to the incident beam. Changes in the observed scattering data as a function of the tilting angle are related to characteristics such as the height of the structures and the symmetry of the line shape.

A DualBeam Metrology system was investigated for the application of obtaining 3-dimensional (3D) characterization of a 130 nm ground rule KrF photolithography process. Integrated circuit devices are 3-dimensional in structure and, hence, should be best characterized using 3-dimensional techniques to ensure adherence to the design architecture and the desired process window for manufacturing. The need for 3D metrology is further required for the characterization and monitoring of critical layer processes and equipment performance. The metrology used in this investigation is a novel technique for critical feature cross sectioning. The process for DualBeam metrology uses a focused ion beam (FIB) for milling or cutting the cross section through the photoresist or process film. An integrated scanning electron microscope (SEM) provides high-resolution imaging of the features, and a flexible automated metrology package collects and analyzes the data. To demonstrate the feasibility of the technique, critical dimension (CD) data and sidewall angle (SWA) measurements were captured from 130 nm lines and 150 nm contacts at 1:1 densities. The critical criteria for the characterization of the photolithography process window are CD control, depth of focus (DOF), exposure latitude, and feature sidewall angle or profile. Using the DualBeam technique, 2D and 3D data are captured on a single machine platform using a cut, look, and measure routine. A further benefit is the availability of high-resolution cross-sectional SEM images that can be used qualitatively to validate the quantitative data. The results presented here show the performance of this 130 nm ground rule process and the benefits of utilizing this efficient characterization technique.

Scatterometry is an optical measurement technology based on the analysis of light scattered, or diffracted, from a periodic array of features. It is not an optical imaging technique, but rather a model based metrology that determines measurement results by comparing measured light scatter against a model of theoretical scatter signatures. Angular scatterometers in particular function by scanning the features to be measured through a range of incident angles, and measuring the light scattered into the zeroth, or specular, diffraction order. Prior work in angular scatterometry used the technique for the measurement of line profiles in resist and etched materials. In this work applications of scatterometry for the measurement of asymmetric line profiles (unequal sidewall angles, for example) are presented. Beginning with simulated results form the theoretical model, the importance of measuring through complementary (positive and negative) angles of incidence will be demonstrated. Then, actual measurement data from three different sample sets will be presented. The results show that the method has good sensitivity for measuring line asymmetry, and can therefore be used for qualifying processes for which symmetric results might be desired, such as lithography and etch processing.

In the work reported here, we discuss the measurement precision of two scatterometry techniques, the variable angle and the variable wavelength techniques. The issue of interest is the measurement precision of the sample parameters. This is determined by both the sensitivity of the diffraction measurable to changes in sample parameters and the precision with which the measurable can be determined. This approach includes taking into account the correlation effect between the contribution to the measurable of the various grating parameters to be determined, such as linewidth and height. The comparison of the theoretical predictions of precision for angle-resolved and wavelength-resolved scatterometer measurements shows no conclusive hierarchy. Practical considerations, however, indicate that angular-resolved scatterometry is a more advantageous technique. For both methods, decreasing the wavelength of the light source improves the determination precision of the sample parameters.

Smaller device dimensions and tighter process control windows have created a need for CD metrology tools having higher levels of precision and accuracy. Furthermore, the need to detect and measure changes in feature profiles is becoming critical to in-line process control and stepper evaluation for sub-0.18micrometers technology. Spectroscopic CD (SCD^TM) is an optical metrology technique that can address these needs. This work describes the use of a spectroscopic CD metrology tool to measure and characterize the focus and exposure windows for the process. The results include comparison to the established in-line CD-SEM, as well as a cross-section SEM. Repeatability and long-term stability data form a gate level nominal process are also presented.

Phase-modulation scatterometry is a metrology technique for determining the parameters of gratings using as a key device a phase modulator. For measurement purposes the phase modulator requires a complicated calibration procedure that is analyzed here in detail. The main source of error to be dealt with are the fluctuations of the phase modulation amplitude. The measurables are the direct term and the first two harmonics of the output. For the fitting of the experimental data we used the ratio of the harmonics to the direct term because it improves significantly the accuracy. A sensitivity analysis was performed for two samples, one real and one theoretical, to find the measurement configuration that insures optimum determination precision for the grating parameters. For the real sample, comparisons of the theoretical predictions for sensitivity with the actual values showed a good agreement. For both samples the sensitivity analysis indicated sub-nanometric precision for the critical dimension (grating linewidth).

In this paper we introduce the concept of single combined field integral equation to the rapidly developing field of in-line metrology employing scatterometry. The new method is very fast and accurate with extreme versatility, enabling very rapid profile analysis of periodic and isolated features. Several examples in 2D and 3D, such as T-top profiles, contact holes and entire SRAM cells, are presented.

Simple microeconomic models that directly link metrology, yield, and profitability are rare or non-existent. In this work, we validate and apply such a model. Using a small number of input parameters, we explain current yield management practices in 200 mm factories. The model is then used to extrapolate requirements for 300 mm factories, including the impact of simultaneous technology transitions to 130nm lithography and integrated metrology. To support our conclusions, we use examples relevant to factory-wide photo module control.

We describe a novel, IR phase shifting Haidinger fringe interferometer for measuring the thickness, total thickness variation (TTV) and bow of silicon wafers. We show that by taking 3 interferograms of the wafer in different positions in the cavity it is possible to separate thickness, TTV and bow. We also show that bow has an effect on the measurement of TTV.

Integrated circuits are becoming more sensitive to overlay errors between the most critical layers. This paper focuses on inter-transistor overlay variations, which are defined as the short-range variations of overlay between transistors separated by distances of 1 micrometers to 100 micrometers . Many circuits are particularly sensitive to these inter- transistor variations. However, inter-transistor variations are difficult to measure using conventional techniques of metrology. We have developed an active electrical metrology method using on-chip test circuitry to map inter-transistor overlay variations. Test chips were designed and fabricated on a commercial HP 0.35 micrometers process. An array of 127 x 64 active electrical overlay test structures was measured. The array has an area of 856.8 micrometers x 705.6 micrometers , with uniform sampling spacing of 6.8 micrometers x 11.2 micrometers . A measurement speed of 5 microsecond(s) per site was achieved with an accuracy of 6.5 nm (3-sigma). The measured overlay variations between gate poly and diffusion were found to be made up of alignment errors probably associated with the wafer stepper operation combined with short-range overlay variations probably contributed primarily by the mask. With 3-sigma values of 20-30 nm, the inter-transistor overlay variations are surprisingly large when viewed in the context of the typical overall overlay budget for a 0.35 micrometers process. Contour plots and Fourier analysis show that they have an obvious periodicity of 102.4 micrometers in y direction, which can be related to the writing stripes of the raster-scanned mask lithography system used to fabricate the masks. Intra- stripe and stripe-to-stripe overlay variations are then decomposed by spatial frequency filtering, and the intra- stripe variations are further analyzed.

Accurate overlay measurements rely on robust, repeatable, and accurate feature position determination. In our effort to develop traceable overlay standards we have examined a number of edge detection methods and the parameters which affect those measurements. The samples used in this study are a comprehensive set of prototype overlay wafer standards. The methods for determining the position of a feature generally rely on some determination of edges, and the resulting feature centerline can be significantly affected by the method of choice. We have compared cross- correlation, centroid, and edge-threshold methods as well as an integrated least squares method. This paper is focused on empirical results obtained through the measurement of relevant overlay targets and pitch specimens. The data presented in this paper was acquired using charge coupled device (CCD)-based arrays.

The NanoWave Scanning Probe Position Encoder (SPPE) is a real-time position measurement device developed for next generation nano-scale positioning applications. The performance level sought is: 1nm precision over 300mm, 0.01nm resolution, and a detection speed of 5-10 m/sec all simultaneously. These devices use holographic gratings as reference scales in conjunction with Scanning Probe Microscopy (SPM) technologies, which may include focused beams as probes, and a patented phase-tracking detection method. The SPPE sensor probe is oscillated near its resonant frequency above the (100nm - 300nm period) holographic grating surface while it scans the grating across the grating land and grooves. This generates the output with high-order harmonics of the probe oscillation, which contain quadrature signals corresponding to the position information. The peak-to-peak amplitude of the probe scanning range at the resonant frequency needs to be only a little larger than a grating period for stable gap distance control, high precision oscillation control and low heat generation. Furthermore, high probe oscillation frequency allows decoupling the position measurement in X and Z directions, maintaining enough bandwidth in each axis measurement, leading to a unique multi-axis position measurement capability.

The optical behavior of semiconductor bottom antireflective coating (BARC) material was investigated by both the measurement and simulation methods. The effects of spin- coating rate, interface reflection, BARC layer thickness and photoresist layer thickness were studied. Our results indicated that the 62.5 nm of BARC layer had strong effect on suppressing the light reflection of wavelength of 248 nm form the wafer surface, irrespective of the photoresist layer thickness. Based on the gravimetric method, a high throughput and one-step microwave digestion procedure was developed for the BARC materials. The digestion efficiency increased with the digestion duration and the temperature. By following the established one-step microwave digestion method and inductively coupled plasma mass spectrometry determination, the detection limits obtained for Cr, Ni, Cu, An and Pb were in 0.1 to 1.11 ppb levels. The spike recoveries of the metallic impurities were in the range 86- 102% for the BARC materials. The analytical results of the BARC samples were found to be in reasonably good agreement with our previous method, and the analytical throughput can achieve up to 20 samples per hour for the analysis of 5 elements.

As semiconductor design rules decrease, tighter tolerances are required for alignment. Improvement of the measurement algorithm can make a considerable contribution to reduction of the overlay error. An algorithm makes the alignment accuracy greatly improved that utilizes wavelet transform and uses information about image asymmetry. Experimental result using the Alignment Data Logging System shows that there is a process that the algorithm reduces the overlay error from over 100nm (3(sigma) ) to under 50nm. Two other algorithms are also introduced that are an interpolation method that reduces error from image sampling and a mark recognition method that reduces measurement failures focusing on some kinds of symmetry of the alignment mark.

A new semiconductor material formed by ion beam mixed and implanted metal films on polymer thick films on polymer thick films has been studied. The potential advantage of these materials over commonly used electronic materials is that a wide range of electrical properties can be controlled using processing conditions. The thin metal mixing layer on the surface of the polymer thick film is formed using evaporation and microlithography. The materials can be synthesized monolithically on Si, making them good candidates for use in microelectronics. Ion beam mixing of the polymer with metal film is done by ion implantation through the metal film. The resistivity is reduced compared to the resistivity of ion implanted polymers without the metal layer on the surface. The electrical conductivity demonstrates semiconductive behavior by decreasing with increasing temperature. The resistance and temperature coefficient of resistance increase with increasing thickness of the metal mixing layer. Coulumb Gap (CG) and variable range thermal hopping (VRH) theories are used to fit the temperature dependant experimental data. Results indicate that the thin Cr layer samples are better described by the CG model; while the thick Cr layer materials demonstrate VRH conduction. A model, dependent on the pre-implant metal layer thickness, for the electronic conduction in these unique non-implanted metal-mixed polymer systems is presented.

Contamination control is particularly important in lithography processes because pattern defects are converted to wafers after each exposure. Contamination, by definition, is undesired matter or energy, which causes product defects or process instabilities, and, consequently, reduces yield and reliability. In lithography processes, particles, condensable hydrocarbosn, base molecules, moisture, and static electricity are examples of contaminants. Particles are inert minute objects, which interfere with the proper formation of circuit features. Condensable hydrocarbosn may cause optics hazing which reduces image homogeneity and energy transmission. Some Chemically Amplified Resists (CAR) are susceptible to molecular base contamination, resulting in image degradation such as T-topping. Moisture can affect the characteristics of photoresist, destabilizing photo-exposure and development processes. In combination with water, amine containing photoresist strippers can form hydroxyl ions that can attack aluminum and aluminum-copper alloys. Charged surfaces can tract and hold contaminants of opposite polarity. In case the electrical field exceeds the dielectric strength, ESD event occurs, often accompanied with damage of reticles, masks, or wafer circuits. With SMIF isolation technologies, yield loss due to defects and/or instabilities is minimized. Reticles, masks, and wafers are isolated form contamination sources through hermetic seal, in conjunction with particle/chemical filtration, and static shielding. Pressurization, inert gas purge, chemical absorbents, and electric grounding or air ionization are techniques of removing contaminants from the critical areas. For best performance, adequate selection of construction materials is critical. This paper discusses impacts of contamination on lithography processes and the possibility of solving such problems using SMIF isolation techniques. Theoretical models are developed and experimental data are presented.

Reduction of defects after development is a critical issue in photolithography. A special category of post development defects is the satellite defect which is located in large exposed areas generally in proximity to large unexposed regions of photoresist. We have investigated the formation of this defect type on ESCAP and ACETAL DUV resists with and without underlying organic BARCs, In this paper, we will present AFM and elemental analysis data to determine the origin of the satellite defect. Imaging was done on a full-field Nikon 248nm stepper and resist processing was completed on a TEL CLEAN TRACK ACT 8 track. Defect inspection and review were performed on a KLA-Tencor and Hitachi SEM respectively. Results indicate that the satellite defect is generated on both BARC and resist films and defect counts are dependent on the dark erosion. Elemental analysis indicates that the defects are composed of sulfur and nitrogen compounds. We suspect that the defect is formed as a result of a reaction between PAG, quencher and TMAH. This defect type is removed after a DIW re-rinse.

Wafer-induced-shift caused by bottom anti-reflective coating (BARC) was observed during the misalignment compensation of stepper. This was represented as wafer scale component, that is, shot position dependence across the diameter of the wafer. Measurement error was quantified by comparison between pre- and post-etch pattern alignment data. Typical wafer scale value difference of 0.2ppm in 200mm diameter wafer was observed corresponding to maximum 20nm misalignment in the wafer edge. This is a detrimental value in critical mask step of current device manufacturing, and can be even more serious in next generation design rule adopting 300mm wafer, meaning maximum 30nm false measurement in the wafer edge. To reveal the cause of this phenomenon, the same sequential evaluation was performed without BARC application. No corresponding effect was detected supporting that BARC really caused such wafer-induced-shift. It was found that the wafer-induced-shift amount could be correlated with the size and shape of the alignment monitor pattern. We concluded that the wafer-induced-shift could be minimized by careful adoption of the alignment mark.

Resist swing curves have been constructed practically, and by lithography modeling, for a conventional I-line resist both for dimensions at the substrate interface and at the top of the resist. Top SEM linewidth measurements were difficult to take repeatably in automatic mode so an enhanced measurement technique was developed. The effect of stepper focus on swing curve amplitude has been studied and, for substrate dimensions, amplitude increases as focus moves away from its optimum setting.

Charging effects on secondary electron (SE) profiles with bias voltage in deep contact holes are investigated. We show first in detail the SE beam profiles for operating conditions such as scanning time, current and landing energy, the brightness of the bottom of the contact hole depends on the charge of SE yield with incident energy. We conclude that we can enhance the contrast of the beam profile by optimizing the applied bias voltage.

Misregistration occurs to some extent at every printed point on a wafer due to several causes. Intrafield distortion is one aspect of misregistration that is difficult to detect and resolve in a production environment. Historically intrafield distortion was primarily detected by external overlay measurements of box-in-box structures. Distortion data can also be generated via in-situ pattern placement measurements of scanner/stepper alignment marks. In state-of-the-art exposure tools the magnitude of non-correctable intrafield errors has become small due to advances in lens manufacturing, and tool controls. This increase in quality has caused us to re-examine the capability of current distortion measurement techniques and their correlation to product imaging. This paper presents a comparison of distortion measurement techniques for current DUV scanners and steppers. Wafer level distortion errors were gathered via scanner in-situ mark measurements, LMS IPRO, and CD SEM product overlay measurements. Correlation of the scanner in-situ mark measurements and LMS IPRO measurement process will be presented. We will present our comparison of the product wafer across field overlay measurements with the results generated from the distortion measurements. Our conclusion will attempt to derive a figure of merit for the capability of the customary distortion techniques to describe intrafield product overlay variations.

This work describes how rules for optical proximity correction, derived from lithography simulation, can be favorably changed to improve process latitudes through a metric called a dense-isolated focus/exposure matrix. Example calculations are given to demonstrate the derivation of amended rules.

In recent years electrical linewidth measurement (ELM) has become accepted as an efficient method to gather large amounts of linewidth data rapidly and accurately. However, there are offsets between electrical and SEM measurements. While these have not been a concern for large features, it is important to minimize the bias as the actual linewidth approaches the offset. The purpose of this paper is to demonstrate that ELM can be used to measure linewidths much smaller than 100nm. Our experiments show that out-diffusion and surface ion depletion are the primary sources of bias in electrical linewidth measurement. Silicon nitride capping layers before annealing are helpful to prevent out-diffusion.

The optimization of a dielectric anti-reflective coating (ARC) on a transparent substrate with significant topography is described. Supporting theory is provided and although it is not possible to obtain the ultimate performance of an ARC over planar film stacks and flat substrates, the critical dimension (CD) swing ratio is greatly reduced and a manufactureable solution achieved using response surface modeling (RSM) in combination with data generated form the lithography simulation tool, PROLITH/2.

Commercially available photoresists for 193nm litho technology still suffer of undesired phenomena, which could eventually limit the stability of critical layer processing. Also standard CD-SEM inspection has its impact on the overall litho budget, as the interaction between the primary electron beam and the photoresist locally modifies target dimension. The reduction of this effect can be important to preserve geometrical and also electrical characteristics of the chip, as the local variation of the CD is detectable also after target etching and resist removal. In this paper different strategies to reduce its impact onto production wafers are investigated and compared. By applying a combination of these techniques, CD local modification can be lowered up to 75%.

In a multiple tools environment the matching and stability performance of CD SEM becomes crucial for successful introduction of new technology generations. However proper evaluation procedure for CD SEM precision components represents a nontrivial issue when total precision budget is 1-2nm (according to the National Technology Roadmap for Semiconductors). Factors such as sample damage; process variation and measurement sample size should be carefully examined. In this article we address carryover - a very well known but not widely studied phenomenon, related to the sample damage, which directly affects the precision evaluation of a CD SEM. We have investigated the carryover in an attempt to reduce the effect of sample degradation due to repeated measurement and improve measurement precision. We present results based on relatively large data set and moderate range of variables. The experimental data show that for modern CD SEM both electron energy and current are very important factors defining the carryover. Although no complete elimination of the carryover effect have been observed under the conditions studied recommendations have been made with respect to acceptable compromise based on the current precision requirements.

For higher density devices electric performances have been focused more than the others. In the case of metal sputtering process some of machine makes local asymmetric deposition across the wafer. In this study, a couple of overlay reading errors which comes from asymmetric metal deposition has been studied in terms of photo process. As a result, scaling error could be reduced down to a certain amount with the optimization of overlay reading marks. However it will not be cleared no matter what kinds of mark are used as long as overlay marks are asymmetry. A symmetric sputtering should be the only way to figure out this problem. In order to make total product, related processes have to be concerned as well.

The bulge testing technique determines the mechanical properties of solid thin films by measuring the deformation that forms in response to the application of a controlled differential pressure to a thin film window. By comparing the pressure-displacement relation with a mechanical model, the elastic modulus and residual stress in the film can be measured. While the bulge testing technique can be quite effective, the technique is not routinely used because of difficulties that often arise with using this technique. The difficulties include specimen preparation and mounting, automated bulge height measurement and the correlation of bulge deformation with the mechanical properties of the thin film. This paper describes developments in the bulge testing technique that alleviate many of these difficulties, as well as presenting results from the testing of single and dual layer thin films. Single film tests were conducted on samples of B-doped-Si, SiC, and diamond-like carbon. A total of 135 windows with three different window aspect ratios and two different thicknesses were investigated. In a preliminary study to determine the feasibility of extending the technique to the testing of multilayer films, the mechanics of a dual layer system were measured. The dual layer system was an Al layer on top of B-doped-Si. The results from the single film test were that the elastic moduli of the B-doped-Si were close to nominal bulk values and the diamond-like carbon was about half that of diamond. The SiC elastic moduli measurements were inconclusive because of the large prestress. Elastic moduli measurements from nanoindentation were about 50% higher. It should be noted that neither the variation of the aspect ratio nor the variation of the film thickness led to different results. The measured prestresses agreed quite well with wafer curvature measurement. The dual-layer measurements yielded values for the elastic modulus of thin film Al that were within 5% of the nominal bulk values.

In addition to stability and collapse issues facing 193 nm resists, a new concern is rising regarding line width decrease when exposed to an electron beam (e-beam) during CD measurements using scanning electron microscope (SEM). Such an interaction between the measurement system and sample materials poses a great challenge in process development for 193 nm lithography which is believed to be next lithography node. This paper reports the investigation results of 193 nm resist line width slimming under e-beam. We have observed vertical, as well as lateral 193 nm resist shrinkage under e-beam exposure using VeraSEM 3D's unique sidewall imaging technology. We have observed different CD changing behaviors for lines and spaces, as expected. Repeated SEM CD measurements on space magnify the CD changing effect due to 3-5 times more resist exposed to the d-beam than a line. Hence, the influence of other competing effects form line edge roughness, carbonization etc. are reduced. By measuring a space or an edge width at a tilted view, the severity of resist shrinkage of different resist types can be compared directly with a high level of confidence.

As the minimum feature size shrinks to 130nm region, attenuated phase shift mask (attPSM) with optical proximity correction (OPC) is reportedly as one of the potential methods to achieve manufacturable process by using 248nm exposure wavelength. For a typical mask making process, sometimes it is necessary to perform mask repairs to remove unwanted defects. Repairing either the OPC features or the attenuated phase-shifting main features present a new challenge in the mask making process. For both clear and opaque types of imperfect repairs, the repaired edge placement accuracy and/or transmission and phase shirt matching after repair may cause considerable amount of changes in the aerial images and then be transferred into resist patterns. Some imperfect repairs may become killer defects while others can significantly reduce the lithography process latitude, especially around the forbidden pitches. In our study, the effectiveness of defect repairs for 130nm gate attPSM at different pitches is assessed by direct examination from printed wafers.

Scatterometry is a non-destructive optical metrology based on the analysis of light scattered form a periodic sample. In this research angular scatterometry measurements were performed on three wafers processed using shallow trench isolation (STI) technology. The periodic features that were measured on these wafers were composite etched gratings comprised of SiN on oxide on Si. The wafers were processed at three different etch times in order to generate different etch depths (shallow, nominal and deep). It was at this point in the process that the scatterometry measurements were performed. The scatterometry model was comprised of four parameters: Si thickness, SiN thickness, linewidth and sidewall angle. For comparison purposes measurements were also performed using a critical dimension scanning electron microscope (CD-SEM), a cross-section SEM and an atomic force microscope (AFM). The results show good agreement between the scatterometry measurements and the other technologies.

Decreasing dimensions of features in semiconductor device manufacturing makes it imperative to control the sidewall, line and line-edge roughness. The roughness contributes to the variation in critical dimension (CD) and it might affect device functions and reliability. Roughness of vertical surfaces is needed in order to understand its effect on the performance, especially in the case of structures such as optical wave-guides. One of the ways to measure the sidewall, line and line-edge roughness is to use a scanning probe microscope. By using specific techniques in operating the scanning probe microscope and special analysis, we obtain the sidewall, line and line-edge roughness. We also use high-resolution image of the sidewall to characterize its roughness with various techniques including spatial frequency analysis. Both qualitative and quantitative evaluations are demonstrated. These measurements are made with an automated tool in a non-destructive fashion and are useful in production control.

Foot (bottom corner) characterization of a trench or a line in semiconductor processing is of high interest to set and follow processes. The scanning probe microscopes (SPM) available at the present time are not capable of obtaining this measurement. Conventional atomic force microscopes (AFM) are not able to measure the shape of the foot of a trench or a line due to scanning algorithm and probe shape. Even CD-AFM performed with 2 dimensional servo code and boot shaped tips is limited in its ability to make this measurement if the corner is sharper than the radius of the corner of the boot tip used for measurement. We use an extra sharp probe (full cone angle 5 degrees or less) and a technique to tilt the sample to get at the foot of the structure to be measured. We are able to scan this corner of the structure and are able to characterize it by various techniques such as surface roughness. In addition, sidewall, line and line edge roughness can be addressed using the same technique. This characterization can be performed automatically and set as a production control.

Atmospheric pressure deep UV lithography using fast chemically amplified photoresists will be the mainstay of semiconductor production into the foreseeable future. Airborne molecular contamination (AMC) in the form of bases and condensable organic and inorganic materials however, threaten both sensitive optics and modern resists thereby creating a host of yield limiting contamination issues. Past work by Kunz at MIT has described photo-induced organic contamination of lithographic optics as a significant concern in leading-edge lithography. Moreover, Kinkead and Ercken, and Kishkovich and Dean have published work on the impact of base contamination on CD uniformity in modern photoresists. Herein, the authors discuss solutions to control both optics and resist contamination in a single compact filter system for advanced lithography. The results of this work suggest that resist and optics contamination can be controlled as we enter the era of low K1 factor <150nm/300mm-device production.

In this study, a calibration was conducted on an IVS120 optical CD tool (Schlumberger) to define the measurement accuracy for the photo layers in MESFET and HBT processes. Feature sizes varied form 0.85 to 6.0(mu) and the resist film thickness between 0.9 ~ 4.3 micron. It is a challenging task to measure a thickfilm resist feature with a Coke Bottle/T shaped sidewall profile. Various sidewall profiles and the correlated focus/measurement algorithms were studied, especially for the 4(mu) thick HBT implant mask layers. Then a gauge repeatability and reproducibility (GRR) studies were conducted for the IVS120 data after matching to CD SEM to insure the precision of the CD measurements. As a result of this work, the correlation coefficients obtained between multiple runs of measurements were greater than 0.99 on both the reference CD SEM and the IVS120 tool. Standard deviation (3 sigma) was within the specification of the CD tool (1% or 15nm whichever is greater), and approximately 98% maintained within 0.01 micron. Overall GRR was as low as 5-8% in the selected layers and CD ranges.

In a 6 inch GaAs IC fabrication process, a resist liftoff technique was employed to provide definition of features in evaporated metal. The re-entry (overhang) of the resist profile for liftoff, defined by the differences between the top and bottom of the openings, is very critical; in order to protect the defined areas from residual edge metal deposition it is important that the re-entrant profile maintains sufficient overhang to shadow the metal deposition below the edges of the top opening. It is therefore desirable to get the critical dimension (CD) differences of the re-entry measured so that one can monitor the performance of the process form wafer to wafer/lot to lot instead of inspecting irregular wafer samples using the destructive cross section SEM. A methodology was established for this purpose, using a fully automated IVS120 optical CD system, with a study on the application of the focus, measurement algorithms provided by the CD tool. In this work, we resist the profiles with about 0.1 ~ 0.25 micron re-entry at each side were studied and a calibration performed on the optical CD system using cross section SEM as a reference tool. Gauge repeatability and reproducibility was studied before release the method to production line.

This paper describes the design and implementation of a system for monitoring the performance of several major subsystems of a critical dimension measurement scanning electron microscope (CD-SEM). Experiments were performed for tests involving diagnosis of the vacuum system and column stability by monitoring of the following subsystems and associated functional parameters. These include: 1) Vacuum system with pressure as a function of time being recorded for the electron-optical column (gun chamber), the specimen chamber, and the sample-loading unit. 2) The action of several components of the wafer handling system can be timed. 3) The electron gun emission currents and other signals to monitor the characteristics of the condenser and objective lenses may be used to correlate with image quality. 4) Image sharpness, electron beam current, signal-to-noise ratio, etc. can be evaluated.

This paper describes the design and implementation of a system for monitoring the performance of several major subsystems of a critical dimension measurement scanning electron microscope (CD-SEM). Experiments were performed for tests involving diagnosis of the vacuum system and column stability by monitoring of the following subsystems and associated functional parameters. These include: 1) Vacuum system with pressure as a function of time being recorded for the electron-optical column (gun chamber), the specimen chamber, and the sample-loading unit. 2) The action of several components of the wafer handling system can be timed. 3) The electron gun emission currents and other signals to monitor the characteristics of the condenser and objective lenses may be used to correlate with image quality. 4) Image sharpness, electron beam current, signal-to-noise ratio, etc. can be evaluated.

The use of low K1 lithography to extend Moore's Law has been shown to have large implications for random logic design rules. In this work we are continuing the analysis of process control and design rule implications of low K1 lithographic systems to include highly optimized illumination and reticle enhancement conditions. Recent 248nm and 193nm lithography results have shown considerable improvements in two-dimensional pattern transfer linearity from optimized off-axis illumination. Due to the public unavailability of leading-edge layout rules (because of their extremely proprietary nature), we are applying our analysis to the simple lambda based design rule system of Mead and Conway. We analyze the impact of K1 and optimization method by comparing the (normalized) area of a typical SRAM bitcell redesigned according to these lambda based rules. The area of the bitcell strongly depends upon the design rules required for each enhancement technique and K1 factor to achieve a manufacturable cell. These area comparisons allow for easy viewing of the cost of pursuing different low K1 strategies. The results of this work are mainly generated from simulation but are backed by experimental verification from recent 193nm tool and process developments.

Photoresist line edge roughness (LER) has long been feared as a potential limitation to the application of various patterning technologies to actual devices. While this concern seems reasonable, experimental verification has proved elusive and thus LER specifications are typically without solid parametric rationale. We report here the transistor device performance impact of deliberate variations of polysilicon gate LER. LER magnitude was attenuated by more than a factor of 5 by altering the photoresist type and thickness, substrate reflectivity, masking approach, and etch process. The polysilicon gate LER for nominally 70 - 150 nm devices was quantified using digital image processing of SEM images, and compared to gate leakage and drive current for variable length and width transistors. With such comparisons, realistic LER specifications can be made for a given transistor. It was found that subtle cosmetic LER differences are often not discernable electrically, thus providing hope that LER will not limit transistor performance as the industry migrates to sub-100 nm patterning.

Critical dimension (CD) metrology as practiced in semiconductor industry displays characteristics not observed in other metrology disciplines. This paper will present some of the unusual aspects of CD metrology and attempt to elucidate the causes for the observed behavior. Through an examination of the characteristics of measurement accuracy, it is possible to observe these situations where CD metrology departs from the ideal. The typical process for achieving accuracy involves the use of certified standards in a well-defined calibration procedure. However, calibrating CD instruments with linewidth standards will not necessarily guarantee sufficient accuracy of subsequent measurements of production samples. This well-known result follows from lack of physical models to relate the detected signal to sample shape in combination with the many-to-one nature of the mathematical mapping that describes the process of obtaining CD from feature shape. Despite this limitation, monitoring tools such as CD-SEM systems have demonstrated to be useful for process control and are extensively used in semiconductor manufacturing. The requisites for a well-behaved measurement process will be described in detail. The unusual characteristics of CD metrology will be identified, as will the underlying reasons for the behavior. These results will be examined in the light of common process control techniques to explain how CD-SEM measurements still add value despite the flaws. In conclusion the role and value of certified standards in feature shape determination will be placed in the context of CD metrology. Reference Measurement Systems in conjunction with calibration standards are recommended to characterize process variations and determine feature shapes across a variety of samples. In order to ensure that the high throughput monitoring metrology tools flag process excursions for not meeting specifications, feature shapes must be quantified with additional metrics besides a single number CD.

The lens heating (LH) induced focus drift of the ASML i-line Step & Scan was measured at five NA/Sigma settings: three ASML default and two TSMC production settings. The new LH scaling constants at three ASML settings, when multiplied by a dose-matching factor for production, agreed well with the default constants. Experimental results at NAI11 of 0.21 - 0.228 indicate that the LH induced focus drift is NA dependent, and the extent is NA = 0.4A ~ 0.5B>0.63 - 0.65. At the TSMC production settings of NA = 0.4A and 0.5B, the focus drift is approximately 20% greater than those predicted by the ASML LH algorithm. This study applies the new set of scaling constants for the LH focus correction. Long-term focus stability can be maintained within three standard deviations of less than 70nm, for all i-line Step & Scans in the manufacturing environment of one TSMC Fab.

All scanning electron microscope-based inspection instruments, whether they are in a laboratory or on the production line, slowly lose their performance and then are no longer capable of providing as good quality, sharp images as before. Loss in image quality also means loss in measurement quality. Loss of performance is related to changes in the electron source, in the alignment of the electron-optical column, astigmatism, and sample and electron optical column contamination. Detecting a loss in image sharpness easily reveals this decrease of performance. Reference Material (RM) 8091 is intended primarily for routinely checking the performance of scanning electron microscopes. RM 8091 is designed for use in conjunction with Fourier analysis software such as the NIST/SPECTEL² SEM Monitor Program, the NIST Kurtosis program, or the University of Tenesse SMART program. This RM is supplied as a small, approximately 2 mm x 2 mm diced semiconductor chip. RM 8091 is designed to be mounted onto a so-called drop-in wafer for specialized wafer inspection or dimensional metrology scanning electron microscopes or put on a specimen stub for insertion into laboratory scanning electron microscopes. This Reference Material is fully compatible with state-of-the-art integrated circuit technology.

The vacuum systems of all scanning electron microscopes (SEMs), even in the so-called clean instruments, have certain hydrocarbon residues that the vacuum pumps do not effectively remove. The cleanliness of the vacuum and the amount and nature of these residual molecules depends on the type of the pumps and also on the samples moved through the system. Many times, the vacuum readings are quite good but the electron beam still leaves disturbing contamination marks on the sample. This means that in a critical dimension (CD) SEM, repeated measurements cannot be done without extra, sometimes unacceptably high measurement errors resulting from carry-over. During the time necessary for even one measurement, the sample dimension can change, and the extent of this change remains unknown unless a suitable contamination deposition measurement technique is found and regular monitoring is implemented. This paper assesses the problem of contamination of carbonatious materials in the SEM, shows a possible method for its measurement and presents a promising solution to the contamination deposition problem.

Conventional interferometric testing of the flatness of photomask substrates is rendered difficult by the long coherence length of the HeNe laser sources typically used in commercially available phase measuring interferometers appropriate for flatness testing. The Ritchey-Common configuration allows testing of flats in a spherical wavefront; this paper shows that, under appropriate conditions, high resolution surface flatness maps of photomask substrates may be obtained using instrumentation currently available in many optical shops.

As semiconductor devices continue to shrink, precision and stability for the CD-SEM has become increasingly important. Given today's critical dimension (CD) measurements for DUV and sub-DUV process control and development. In particular: maintenance and monitoring of tight tolerances for, tool-to-tool, and across-fab CD-SEM matching have quickly become mandatory for chip manufacturing and development. KLA-Tencor continues to improve its measurement precision and tool automation capabilities for its 8XXX CD-SEM. For 0.25um processes and larger, current tool monitoring procedures are sufficient; however, for processes smaller than 0.25um, the demand for better system monitoring has become increasingly critical especially in multiple CD-SEM matching. In this paper, we incorporated the KLA-Tencor 8XXX CD-SEM Pattern Qualification Confirmation (PQC) for automated monitoring of CD-SEM image quality. Furthermore, we characterized patterned and etched wafers on a Polysilicon substrate. The characterization of electron-beam induced CD growth on various size line widths and pitches will be reported. From the results, we will determine the optimal substrate and pitch size for long-term CD monitoring of CD-SEM.

As critical-feature patterning processes increase in complexity and sensitivity, conventional critical dimension (CD) measurements may not afford the level of process control required for effective device production. By comparing recorded top-down scanning-electron-microscope (SEM) images to a predefined reference image, Pattern Quality Confirmation (pQC) enables a more detailed analysis of measurements captured by KLA-Tencor 8XXX series scanning-electron microscopes. An example of the utility of this additional information is discussed below for a metal interconnect level patterned with a conventional deep-ultraviolet (DUV) photolithography process. In particular, we demonstrate that for certain ranges of focus-exposure conditions, conventional post-develop CD measurements remain well within specification, however, when etched, the resulting metal-line CDs are significantly below the lower specification limit. The pQC image analysis results, however, predict the observed post-etch CD variations, and consequently offer sensitivity to yield-limiting focus drifts and excursions, enabling effective product-dispositioning (rework) decisions.