This PDF file contains the front matter associated with SPIE Proceedings Volume 12955, including the Title Page, Copyright information, Table of Contents, and Conference Committee information.

Without critical dimensional scanning electron microscopes (CD-SEMs), modern microelectronics would have tremendously inferior performance and functionality. Since 1984, their history is closely tied to the phenomenal success of IC technology. Over the decades CD-SEMs rightly became indispensable for process development and control. The future of CD and other SEMs in the IC industry is bright, even if some of their physics limits are not very far away. A great deal of improvements can still be made, but the advancements require complete optimization of electron beam, its scanning, the sample-electron interaction, and the detection of generated signals.

With the explosive growth of artificial intelligence (AI) has come an immense and growing computational burden that is outpacing the rate of traditional logic scaling. To tackle this challenge, IBM is pioneering an analog in-memory compute (IMC) technology that promises to considerably reduce the energy consumption needed for AI workloads by performing the computation directly in memory using resistive non-volatile memory (NVM) devices. This talk will detail the materials and device innovations that enable analog IMC and the challenges encountered in creating a scalable technology. In particular, the importance of controlling variability for a resistive processing unit will be highlighted. In addition, the novel metrology techniques needed to optimize the performance of the key analog materials will be discussed. It will be shown that by comprehending the materials and stochastic characteristics of the NVM devices and co-optimizing with algorithms and architectures, large improvements in energy efficiency can be obtained.

Extreme ultraviolet (EUV) lithography (92 eV) has recently entered logic and memory high-volume manufacturing to ensure the continuation of Moore’s Law into advanced technology nodes (sub 5 nm). In parallel to advancements in the lithographic system, the development of suitable photoresists plays an equally important role in pushing the boundaries of EUV lithography. Fundamental work on well-established chemically amplified resists (CAR) for EUV as well as the upcoming resists based on metal-organic materials have indicated that the lithographic mechanism is largely governed by electron mediated chemistry. In a simplified model, the electrons emitted upon ionization of the material generate further secondary electrons, which interact with the resist components and induce a solubility switch driven by electron and radiation chemistry. To develop a better performing resist, it is of utmost importance to understand the photoelectron kinetic energy spectrum, secondary electrons and their generation efficiency, and the electron mean free path in the photoemission process. In this work, we use photoemission spectroscopy with a table-top, coherent, 92 eV photon source to shed light on the chemistry driven by photon exposure. The valence band photoelectron spectrum (PES) of an environmentally stable chemically amplified photoresist (ESCAP), as well as a model material for an open-source metal oxide (OSMO) resist were measured using our tabletop EUV photoemission setup. We report the evolution of the PES as a function of exposure dose; capturing chemical changes.

We have studied the gradient of photoacid generator (PAG) concentration across the photoresist (PR) layer. The pristine and after exposure to Extreme ultraviolet (EUV) PR layers were characterized. The model resist employed in this study was a chemically amplified resist (CAR) containing sulfur (S) as part of the PAG. The geometrical information about PR layers and element profiles was obtained by applying a hybrid x-ray reflectivity (XRR) and X-ray standing wave (XSW) data analysis using x-ray using a laboratory Cu Kα1 source. The information about S-profile was retrieved from the combined analysis of angular-dependent XRF measurements of S (the XSW data) and XRR data. We have shown that the XSW technique may efficiently be used for analyses of the geometrical parameters of PR layers and underlayers and for retrieving profiles of S concentration.

Depth profile of the dopant concentration in silicon substrate has a crucial influence on the electric characteristics that defines the device performance, whereas those profile has only been evaluated by destructive methods, most typically Secondary-Ion Mass Spectrometry (SIMS). We applied Terahertz Emission Spectroscopy (TES) that exploits charge carrier drift within the built-in potential structure to p-n junction structure in order to non-destructively extract the information about carrier dynamics and consequently the dopant profile. We prepared samples composed of Boron doped region as a p-Si and Phosphor doped region as a n-Si with a different p-n junction depth, and the TES evaluation was conducted illuminating the pump beam with the wavelength of 400nm. The obtained signals exhibit a clear difference among each sample in spite of the junction depth difference of as small as 15nm. The depth sensitivity of TES measurement was also investigated by utilizing carrier dynamics simulation, and clearly indicates the sensitivity to dopant depth profile, which is consistent with experimental TES signal. These results suggest that TES technology is very promising as in-line dopant profile measurement tool which is currently unrealistic with existing technologies and expected to greatly enhance the process control capability.

A key element of semiconductor fabrication is the precise deposition of thin films. Amongst other aspects, the quality of interfaces between different materials plays a crucial role for the success of further process steps. We here present soft x-ray reflectometry measurements on stacked thin film samples of silicon and silicon-germanium in various concentrations as they are produced for complementary field-effect transistor (CFET) applications. Synchrotron-based, angle- and energy-resolved broadband reflectance data sets can be modeled using a matrix-method approach that describes reflection, absorption, and diffuse scattering off the interfaces. This method is often used to determine the optical constants of materials in the EUV spectral region as parameters of the fitting procedure. We here show that the method is equally well suited to investigate roughness and layer intermixing between different deposited materials. These roughness parameters alongside the actual thicknesses of the individual layers also result from the physical modelling of the measured data. The method is inherently non-destructive and very sensitive, down to approximately 50nm depth and as such gives valuable information. To further qualify our findings, we compare the data to scanning transmission electron microscopy (STEM) and energy dispersive x-ray spectroscopy (STEM-EDX) to give insight into the atomic structure at the interfaces.

This paper demonstrates the successful lab-to-fab transition of dynamic secondary-ion mass spectrometry (SIMS). In comparison to traditional lab SIMS, the in-line version is optimized for automated wafer and measurement sequence handling and high throughput measurements in small areas. Key advantages are fast turn-around time, reduced scrap, increased yield, and the measured wafer can continue processing in the manufacturing line. The benefits of in-line SIMS in the production environment are demonstrated for several use cases: matching and monitoring the long-term stability of epitaxy tools on monitor wafers, process optimization and monitoring of epitaxial Si and SiGe layers on blanket and patterned wafers with blanket metrology targets, measurement of implant and dopant profiles on blanket and patterned wafers, and characterization of the Ge and B diffusion in multi-layer stacks stimulated by high-temperature annealing. Additionally, the characterization of the source/drain epitaxy in a fully integrated nanosheet gate-all-around transistor architecture is demonstrated and discussed. The results are compared to off-line lab SIMS and alternative methods where available.

Here we examine a new methodology for spatially resolved molecular analysis to address an important area of need related to the performance of EUV resists, namely detection of molecular components at a scale below the current 20 nm critical dimension. Analysis consists of stochastically sampling the surface with a suite of nano projectiles each of which results in the emission of multiple secondary ions, SIs, from a volume 10-15 nm in diameter on the surface. The SI detector is a multi-anode detector allowing for the radial and translational energies of each SI to be examined. We tested this new methodology on model line patterned EUV resist materials and found the when bombarding the surface with the primary ion path perpendicular to the line pattern, impacts on top of the intact resist resulted in the emission of SI with high translational and axial energies in the forward direction. In contrast, impacts which occurred on the resist sidewalls results in emission in the backward direction. Thus, by examining the energies of emitted SIs molecular analysis can be undertaken on each part of the pattern (side wall, intact resist, substrate) with high resolution.

The adoption of EUV lithography has enabled the reduction of device dimensions; however, the commensurate scaling of variability, such as line edge and width roughness (LER/LWR), has remained elusive. Understanding the origins of these effects has proven challenging, as they cannot be detected until after the final dissolution step. In this study, we present our recent findings using critical-dimension resonant soft X-ray scattering (CD-RSoXS) to investigate the scattering behavior of photoresist materials. Our primary objective is to gain insights into the contributions of each process step to the generation of LER/LWR as well as footing/scumming. RSoXS capitalizes on tunable soft X-ray sources to significantly enhance the scattering cross-sections from heterogeneous materials. This enhancement provides valuable insights into sub-nanometer spatial resolution and local chemical sensitivity concurrently. To extract a comprehensive profile of the latent image, we employ simulations involving the form factor and subsequent reconstruction of line shapes.

In the field of semiconductor manufacturing, Scanning Electron Microscope (SEM) is employed for critical dimension (CD) measurements, overlay measurements, and defect inspections to ensure the quality and reliability of semiconductor devices. Nevertheless, SEM images inherently carry a significant level of noise, leading to inaccurate metrology and false defect inspections. Therefore, it is crucial to develop denoising techniques. One widely used method is frame averaging, which reduces cumulative noise by averaging multiple scans. While increasing scan times enhances SEM image quality, it comes with drawbacks such as surface charging, pattern shrinkage, and reduced throughput. Deep learning (DL) techniques, including supervised and unsupervised approaches, have shown remarkable progress in the field of SEM image denoising. However, supervised methods are notably affected by phenomena such as pattern shrinkage and surface charging, which occur during the capture of reference images. On the other hand, unsupervised methods are typically more effective with lower noise levels. In this paper, we introduced a flexible DL method for denoising SEM images that operates without the requirement for paired data. To demonstrate its effectiveness, we analyzed and evaluated its performance in two metrology tasks. Experimental results validated the efficacy of our method in reducing noise, demonstrating its applicability to both ADI and AEI.

We propose a robust dynamic spectroscopic imaging ellipsometer (DSIE) as a future high-throughput full pattern wafer inspection candidate in semiconductor MI fields. In this study, we demonstrate a Linnik-type monolithic polarizing interferometer scheme combined with a simple spectrometer-based compensation channel can enhance system robustness and stability drastically. Also, we address the importance of the global mapping phase error compensation method by which highly reliable 3-D cubic spectroscopic ellipsometric parameter mapping capability can be provided for a large-scale specimen. To show the efficacy of the proposed compensation method experimentally, we measure a 12-inch full size silicone-dioxide thin film and a 8-inch nano-pattern wafer in a general environment where various external disturbances can affect the system stability.

Non-destructive nano-metrology is a fundamental tool for semiconductor device manufacturing. Practically, a combination of several metrology techniques is needed throughout the fabrication process of semiconductor chips, from EUV photomask inspection to patterned wafer metrology. EUV light not only facilitates the production of smaller features in lithography but also emerges as a powerful approach for the metrology required to characterize and analyze these intricate features in future technology nodes, thanks to its short wavelength, relevant penetration depth, and high reflectivity with relatively high grazing angles compared to that of x-rays. The reflective grazing incidence nanoscope for EUV (REGINE) at the Swiss Light Source is a prototype platform for reflectometry, scatterometry, and coherent diffraction imaging. It operates in the soft x-ray and EUV region (80 to 200 eV photon energy), and covers a grazing incidence angle range of 0° to 28.6°. REGINE provides the possibility to perform grazing incidence reflectometry and scatterometry for semiconductor metrology. In this study, we present the results of optical constants (n and k) determination and layer thickness characterization with reflectometry procedure for an EUV attenuated phase shifting mask blank, and the analysis of scatterometry results of line-space grating profile reconstruction and overlay measurement.

This paper describes the lateral resolution enhancement of dynamic spectroscopic imaging ellipsometer, aiming to improve its inspection capabilities. Traditional imaging ellipsometers use a rotating optical elements type scheme which typically requires longer acquisition time. Moreover, for spectroscopic applications, an extra spectral scanning mechanism is needed. The proposed system based on a one-piece polarizing interferometric module, can efficiently extract spatio-spectral ellipsometric phase maps of two-dimensional (2D) materials with a spatial resolution of a few microns at a speed of hundreds of Hz.

The thickness of the chalcogenide ovonic threshold switching (OTS) layer is one of the most critical parameters for the switch-only memory (SOM) process control. Traditionally, the OTS thickness and composition were measured by XRF using the amounts of Ge, As, and Se. Still, XRF has a few limitations in delivering the required performance, especially for products with multilayer memory architecture. For these products, x-ray fluorescence (XRF) signals overlap and cannot be used to measure the thickness of each layer. In the current paper, we have studied three new alternative approaches for measurements of the OTS thickness on-cell: Spectral Interferometry, Raman spectroscopy, and Hybrid Machine Learning technique. The first method, Spectral interferometry with the Vertical Traveling Scatterometry approach (VTS), allowed OCD modeling of the top of the structure by blocking the complex underlayers and measuring only the top OTS thickness on all targets, including within the chip. The second method, Raman spectroscopy, demonstrated oncell dimensional capabilities with an excellent correlation of the Ge-Se, As-Se, and Ge-Ge bonds of Raman active chalcogenide to TEM OTS thickness values. Finally, the third method used Raman parameters calibrated with TEM as a reference thickness for the ML solution using the VTS spectra on-cell. This ML method is fast, model-free, and requires minimal TEM samples for setup. All three methods have demonstrated capability for on-cell measurements and HVM process control.

Fourier Transform Infrared spectroscopy offers inline solutions for chemical bonding, epi thickness, and trench depth measurements. Through optical modeling of the transmission or reflectance spectra, information about the electronic structure and chemical composition may be obtained, which can be used for process control and monitoring. In this article, we demonstrate the measurement capabilities of FTIR for the hydrogen bonding in cell silicon nitride and amorphous carbon hard masks (ACHM), which are used for 3D NAND fabrication. For cell silicon nitride, deconvolution of the spectra allows differentiation between individual peaks corresponding to Si-N, Si-H, N-H, Si-O, and Si-OH bonds. This differentiation identifies wafers with varying hydrogen content and distinct processes. Similarly, for ACHM, peak areas related to sp² C-H bonds and aromatic C=C bending reveals the hydrogen skew conditions in three wafers. Notably, a linear relationship between high broadband absorption and low C-H bonds (and aromatic C=C) peak area is observed. The measurements exhibit good repeatability across ultrathin silicon nitride and thick ACHM samples. We believe the technique can be valuable for compositional process control, considering the significance of hydrogen content in cell nitride performance and endurance, as well as the influence of hydrogen content and carbon sp²/sp³ ratio on selective etch ratios in dry etch processes involving ACHM and mechanical properties of the films.

The CHIPS and Science Act of 2022 called for NIST to “carry out a microelectronics research program to enable advances and breakthroughs….that will accelerate the underlying R&D for metrology of next-generation microelectronics and ensure the competitiveness and leadership of the United States….”, NIST is leveraging its measurement science expertise, standards development contributions, and stakeholder engagement practices to address the highest priority metrology challenges identified across industry, academia, and government agencies. The program expands upon NIST’s strong track record of supporting the semiconductor technology and manufacturing ecosystem by developing, advancing, and deploying measurement technologies that are accurate, precise, and fit-for-purpose.

Subsurface Scanning Probe Microscopy (SSPM) complements present optical and electron-beam based techniques (e.g. CD-SEM, x-ray scatterometry, etc.) for measuring through optically opaque layers (for e.g. metals like Ta, W, Ti) by being non-destructive in nature with greater depth sensitivity. With the potential CMOS scaling road-map extension by IMEC presenting Gate All Around (GAA) and Complementary Field Effect Transistors (CFET) as the future of most CMOS devices, there is a rise in stacked 3D architectures with relatively less stiffness difference between adjacent nanostructures. The processing of gate all-around Si transistors requires isolating vertically stacked nanometers-thick Si sheets or wires. For this purpose, the SiGe layers of a SiGe/Si superlattice are etched selectively and laterally. Controlling the quantity of etched SiGe material, i.e., the cavity depth, is critical for optimal device performance. The critical dimension (CD) of the underetch can only be measured by cross-sectional electron microscopy providing limited statistics and hence control of the underetch across wafers. This process also requires more time reducing the overall efficiency. With SSPM, one can sensitively distinguish such cavity structures based on the relative stiffness difference. This process is comparatively faster providing sub nanometers resolution with statistically significant direct local 3D information. This work showcases the enhanced achievable sensitivity in mixed-frequency excitation scheme in comparison to single-frequency excitation scheme in SSPM for distinguishing the critical dimensions of the given samples based on the increasing etch recess. The achieved performance is for distinguishing non-destructively the difference in sub 10nm etch difference lying below a capping layer of approximately 100nm of hard and opaque layer. The top layer can be treated like a gate material due to relatively similar material and physical characteristics. Thus, this work can be treated as an example of subsurface measurements of buried nanostructures through gate like material.

Advanced semiconductor devices are moving toward 3D geometries due to scaling demands and performance requirements. The non-destructive metrology necessary for process control for high volume manufacturing of 3D structures must be advanced to facilitate their transition from technology development to high volume manufacturing. Optical Critical Dimensions (OCD) techniques based on Mueller Matrix Scatterometry (MMSE) as well as XxRay Diffraction (XRD) have proved capable of measuring the Si/Si_1-xGe_x few layer superlattices used to fabricate Gate All Around (GAA) transistor device test structures. The limitations of these techniques associated with superlattice device structures needed to be further understood. To understand the limits of MMSE Scatterometry and XRD, a four superlattice layer Si/Si_1-xGe_x structure was measured as a film stack, a column etched sample, and at two levels of cavity etch. XRD was used to determine individual layer thicknesses and compositions of the film stack, and electron microscope data was used to verify initial structure dimensions for OCD models. First, film stack characterization and metrology for both ellipsometry and x-ray characterization were explored. OCD modeling and measurement strategies were evaluated to address the challenge of fitting the superlattice thicknesses in the stack at different etch levels. We demonstrate the characterization of relevant test structure dimensions, including cavity etch using MMSE-Scatterometry. We also demonstrate an alternate technique, x-ray fluorescence for determining cavity etch on the same structures.

The semiconductor industry has witnessed a fast progression of spectroscopic ellipsometry (SE) techniques aimed at resolving a plethora of complex device characterizations on a nanometric scale. The Mueller Matrix (MM) methodology coupled with rigorous coupled-wave analysis (RCWA) has offered an unprecedented power of investigation and analysis of diverse critical dimensions (CDs), especially when applied to gate-all-around (GAA) structures, as it helps increase the useful spectral signals of the often geometrically buried CDs. However, the sensitivity to the CDs can be often screened by other parameters, hampering the precision and accuracy of the measurement. Combining the most sensitive MM elements has therefore become a critical step of scatterometry critical dimension (SCD) metrology. Driven by the rapid developments of Machine Learning (ML) algorithms, we propose a versatile ellipsometry methodology that overcomes poor sensitivity and increases accuracy through a novel principal component analysis (PCA) method of the ML training algorithm with RCWA assistance. Furthermore, our methodology introduces a new ML training concept based on reference data statistics, rather than raw reference. Our approach has been validated with reference data and proved successful in monitoring GAA sheet-specific indent. The proposed methodology paves the way to measuring low sensitivity CDs with highly accurate, noise-reduced and robust ML-based physical SCD models for any logic and memory application.

CD variation and more specifically, the line edge roughness (LER), on features now dominates the edge placement error (EPE) and can even exceed the overlay error component of EPE as we scale to more advanced process nodes. A method to accurately differentiate between patterning options is required at these dimensions. The measurements must be accurate and not be influenced by the measurement technique or equipment. EUV lithography and the scaling of the dimensions has brought a greater importance to the effects of linewidth roughness (LWR) in device performance. Lithographers today have to spend considerable amounts of time to measure these irregularities coming from stochastic effects as well as chemical reactions, in order to accurately quantify the patterning effects whilst maintaining cost-effectiveness in manufacturing. In this paper we examine usage of unbiased LWR measurements for EUV direct-print patterning of 32nm, 36nm and 72nm pitch gratings to help instruct the proper choice of materials for photolithography, etch process optimization, illumination source selection as well as improved matching of scanner equipment.

Edge Placement Error (EPE) is a construction metric which can be derived from CD (critical dimension), Overlay and LER (Line Edge Roughness) measurements from multiple layers, and is well accepted as a critical metric of patterning control due to the increases of process complexity as the design rule shrinkage of CMOS devices. Historically, these conventional metrics are measured from multiple tools on different patterns and locations; for example – overlay, on an optical tool from scribe-line target at ADI (After Develop Inspection) step, while CD/LER data are measured using a CD-SEM tool on a real device pattern at ADI/ACI (After Clean Inspection) steps. TMU (Total Measurement Uncertainty) increasement, which causes the consistency of EPE analysis, is the major limiting factor with the constructive EPE approach. Hence implementing EPE with the constructive way as in-line monitoring metric is not practical and straightforward way. This limitation on traditional EPE methodology can be overcome through single image-based approach, where EPE is measured directly from the high landing energy see-through image. Another advantage is that in parallel it provides CD, Overlay and local variability measured at once on a real device feature. All-In-One (AIO) means all EPE related metrics (CD, Overlay, LER, EPE metric) are captured with single image, which is inherently delivering TMU of sub nm level. Continuous device scaling requires tighter TMU in patterning process integration and control. Fabrication of complex structures demands extremely precise overlay and critical dimension measurement along the sequential processes which drives to a holistic approach on EPE metrology, which can be enabled by new 3D see-trough measurement where traditionally 2D metrics are given. Thanks to the high-resolution see-through image under high keV e-beam, interlayer 3D-EPE measurements on complex geometries can be precisely captured and analyzed. See-through image at ADI step is enabled with recent developments on higher keV e-beam system. Overlay metrology on real pattern at ADI was demonstrated and shown the overlay NZO (Non-Zero Offset) error decomposition between lithography and other processes. For the ADI EPE analysis, the contour extraction from low contrast image is another key enabler together with design-based metrology. Utilizing ADI and ACI AIO image of high landing energy SEM and the contour metrology, EPE metrics can be measured along the process steps and analyzed through contours to design intent. An illustration of such type of measurements is shown in Figure 1. In this paper, we will first demonstrate EPE analysis using AIO image both ADI and ACI step and, second, show how the potential weak patterns with the consideration of 3D-EPE can be measured and extracted through the combination of the AIO see-through imaging of ADI and ACI and the design-based contour metrology. In the long run, 3D-EPE aware weak patterns needs to be qualified as HVM (High Volume Manufacturing) in-line monitoring EPE metric like the traditional CD and Overlay metrology. These design-based 3D-EPE capability of HVM can be expanded and enhanced with the big data nature in production and the new metrology can be potentially improved with the machine learning based technology.

The grouping method assisted EPE-aware control method is being explored in a multi-feature dual layer Logic use case. EPE metric is estimated using angle resolved optical Scatterometry based overlay and electron beam-based metrology (large field of view SEM) for the reconstruction of edge-to-edge distance between the Metal and Via pattern. In the setup phase, EPE sensitivities to dose and focus have been derived using data from a FEM wafer. EPE-aware optimization, using scanner dose and overlay control sub-recipes, outperforms traditional optimization in simulations showing reduced EPE max per die. This improvement suggests a potential increase in device yield through the adoption of EPE-aware control strategies. To verify this performance improvement on wafers, an experiment is needed with minimal wafer to wafer and lot to lot variations which can be achieved by reducing time between lots and increasing the number of wafers measured.

The Edge Placement Error (EPE) is growing concerns due to the complexity increases of process variation as the design rule shrinkage of DRAM device. The EPE is a well-accepted metric which can be derived from CD, Overlay and LER measurements from more than patterning layers that concerned. Therefore, real time EPE measurement becomes a major factor to monitor and control the pattern fidelity. The pattern fidelity could be found from the edge placement measurement as a distance to design intent as possible without pattern defects. However, the traditional application of photolithography and etch biases according to a design rule or model for identifying pattern fidelity has inherent low TMU, multiple non consistence data sources and time-consuming off-line analysis. In previous works, we demonstrated the innovative e-Beam EPE metrology application using All-In-One (AIO) methodology to comply the required Total Measurement Uncertainty (TMU) and Time to Result (TTR) on the advanced DRAM nodes. AIO imaging and analysis methodology that deconvolute CD, overlay and relevant EPE metrics from a single see-through image is the most important differentiation for this EPE analysis approach. The in-cell direct EPE measurement with All-In-One (AIO) imaging and massive sampling demonstrates the better process controls and monitoring from the co-optimization of multiple control parameters and direct measurement of the yield relevant metrics. In this paper, we would like to show a couple of EPE monitoring use cases which shows good correlation to the final yield map through the massive and multi-layer measurements. Especially, it is expected that the EPE component which measures the edge-to-edge distance between different features of multi-layers can be a useful indicator for predicting yield along with CD and overlay. To investigate the local and random variabilities, which local stochastic effects are contained, we also studied the degree of yield prediction of the EPE component with increasing number of measurement sites in local area. It is proposed that using a large amount of measurement sites allows to improve the yield prediction accuracy to a certain extent, which means the local stochastic effects can be effectively analyzed with the use of massive metrology approach. In addition, from the prediction accuracy study using EPE model-based machine learning, we proved that the EPE is sufficiently sensitive indicator to capture potential yield-loss problems in normal wafer, as well. Therefore, in-line EPE monitoring using AIO metrology enables the root-cause analysis of patterning weak points and provides a better process monitoring/correction solution to enable faster advanced DRAM node development ramp and high-volume stability.

The overlay accuracy for current technology node of 3-D structures has to be precise down to a single-digit nanometer range. At those tiny dimensions, overlay errors can occur in the fabrication process ow, thereby impacting the chip yield and performance. With the current CMOS logic road-map, which involves multiple patterning, achieving more stringent overlay requirements becomes even more challenging. With multiple alignment layers it becomes difficult to have a reference metrology to estimate the error induced. Subsurface Scanning Probe Microscopy involving frequency-mixing scheme is a candidate that can cater to this need of reference metrology due to its ability to measure through several layers non-destructively. In this work, metrology investigation has been carried out on a wafer in which programmed overlay error has been introduced. SSPM is used to estimate the variation in overlay introduced, shedding light on achievable sensitivity and performance while scanning through different layers.

As semiconductor device structures continue to shrink and increase its complexity, the need for precise measurement techniques extends beyond single-layer patterning to encompass overlay and Edge Placement Error (EPE) across multiple layers. Traditionally, overlay and EPE have been managed using dedicated patterns and equipment, respectively. However, as manufacturing processes become more intricate, there arises a necessity to measure these parameters directly on actual device patterns. Addressing this demand, High Voltage-Scanning Electron Microscopy (HV-SEM) emerges as a viable tool for on-device-overlay measurement. Nevertheless, challenges persist in achieving accurate measurements using seethrough Backscattered Electron (BSE) imaging due to low contrast and sharpness resulting from electron diffusion through upper-layer patterns. This impedes precise contour extraction and reduces pattern measurement sensitivity. Moreover, in layouts where pattern contours between layers are closely spaced, precise contour extraction becomes even more challenging. To address these issues, a specialized contour extraction function is essential for achieving precise and stable pattern extraction from BSE images. In this paper, we propose a novel HV-SEM overlay measurement methodology utilizing active contour model with Electron Beam (EB) simulation. Synthetic images, designed to emulate the latest device structures and based on BSE features obtained through EB simulation, were employed for evaluation. The results demonstrate the method's robustness to noise and its ability to accurately extract the contours of partially hidden lowerlayer patterns. The proposed approach will enhance the accuracy of HV-SEM overlay measurements, thereby expanding the utility of HV-SEM see-through BSE imaging in semiconductor manufacturing processes.

This paper characterizes, studies and breaks down different components of OL inaccuracy and NZO for a back-end-of-line (BEOL) metal layer on an advanced node testsite. In this study, NZO is characterized by measuring SEM OL and OM OL at the same locations across the wafer and at various process steps. To understand the root-cause of the NZO, process-induced OL shift on both SEM OL and OM OL from ADI, to AEI and finally to CMP are characterized and discussed. It shows that process-induced OL shift is a major contributor to OL inaccuracy and NZO and is affected by the CD and pitch of the measured feature. This paper also studies OL difference between kerf (where OM OL marks are typically located) and in-die (where actual device are located) overlay. Lastly, OL delta between the two OL measurement techniques was studied by measuring the same OL mark with both SEM OL and OM OL tools. This paper concludes with a breakdown of key contributors to OL inaccuracy and NZO. It provides recommendations and future work on utilizing SEM OL in conjunction with OM OL to address the challenging overlay inaccuracy and NZO requirement for advanced logic node.

Wafer bonding technology is one of the key processes for high density and high performance semiconductor devices. However, bonding pads could not be directly observed with visible light after wafer bonding because of the thick silicon substrate. In this paper, we demonstrated high-precision bonding overlay control techniques using a bonding machine, an advanced process control (APC) system, and a newly developed overlay measurement tool that uses infrared (IR) light. The accuracy of the IR-light overlay measurement was verified by using a conventional visible-light tool after back-side silicon removal. The verification results showed good measurement repeatability and accuracy of the IR-light measurement which can be performed right after wafer bonding.

With the increasing complexity of 3-D semiconductor structures, the use of optical critical dimension (OCD) metrology has become a popular solution due to its accuracy and fast inference time. Machine learning has been widely adopted in this field to further improve the efficiency and precision of OCD metrology. Especially for high aspect ratio structures such as DRAM and VNAND, where the required computing power for physical modeling increases exponentially, the importance of machine learning with reference data is crucial. However, one significant challenge of the machine learning-based metrology under rapidly changing process condition is the limitation of available labeled data, which causes overfitting and decreases recipe reliability in the manufacturing process as the cost of wafer consumption increases. To utilize machine learning algorithms in mass production, the development of robust algorithms that can be optimized with few-shot data is required. In this paper, we propose a few-shot machine learning algorithm that includes i) wafer-level statistical information-based data augmentation and ii) anomaly detection to automatically remove data with measurement errors. The proposed algorithm shows superior accuracy, repeatability, and in-wafer uniformity compared to the benchmark algorithm in tests with manufacturing phase data. Additionally, this robustness can be sustained with the minimum amount of data in metrology, as only 9 reference training data are used on three design of experiment (DoE) wafers. The proposed optimized solution is expected to contribute to the reduction of measurement costs and production yields of highly complicated 3D semiconductor structures.

Continuous progression of Moore’s law brings new challenges in metrology and defect inspection. As the semiconductor industry embraces High-Numerical Aperture Extreme Ultraviolet Lithography (High-NA EUVL), there is a current industry-wide evaluation of this technology for potential pitch reduction in future nodes. One of the primary hurdles in implementing High-NA EUVL in High Volume Manufacturing (HVM) is its low depth of focus. Consequently, suppliers of resist materials are compelled to opt for thin resist and/or new underlayers/hardmask’s. Experimental combinations of thin resist materials with novel underlayers and hardmask’s seem to pose signal detection challenges due to poor Signal-to-Noise Ratio (SNR). In such a scenario, manual classification of these nano-scale defects faces limitations in terms of required time and workforce, and the robustness and generalizability of outcomes are also questionable. In recent years, vision-based machine learning (ML) algorithms have emerged as an effective solution for image-based semiconductor defect inspection applications. However, developing a robust ML model across various image resolutions without explicit training remains a challenge for nano-scale defect inspection. The goal of this research is to propose a scale-invariant Automated Defect Classification and Detection (ADCD) framework capable to upscale images, addressing this issue. We propose an improvised ADCD framework as SEMI-SuperYOLO-NAS, which builds upon the baseline YOLO-NAS architecture. This framework integrates a Super-Resolution (SR) assisted branch to aid in learning high-resolution (HR) features by the defect detection backbone, particularly for detecting nano-scale defect instances from low-resolution (LR) images. Additionally, the SR-assisted branch can recursively generate or reconstruct upscaled images (∼ ×2/×4/×8...) from their corresponding downscaled counterparts, enabling defect detection inference across various image resolutions without requiring explicit training. Moreover, we investigate improved data augmentation strategy aimed at generating diverse and realistic training datasets to enhance model performance. We have evaluated our proposed approach using two original FAB datasets obtained from two distinct processes and captured using two different imaging tools. Finally, we demonstrate zero-shot inference for our model on a new, originating from a process condition distinct from the training dataset and possessing different CD/Pitch characteristics. Our experimental validation demonstrates that our proposed ADCD framework aids in increasing the throughput of imaging tools (∼ ×8) for defect inspection by reducing the required image pixel resolutions.

2D materials hold significant potential for enhancing semiconductor device performance. However, their integration necessitates the establishment of a robust metrology that is both accurate and fast, enabling a comprehensive understanding and precise control of their growth processes. Scanning electron microscopy (SEM) ticks all the boxes to be a promising technique for 2D materials characterization due to its sensitivity to monolayers (ML) and its high measurement throughput. Nevertheless, automating its measurement analysis is essential to avoid slow data processing and inaccuracies in results. In this work, I propose a set of image-processing algorithms to extract various 2D material properties from SEM images and reveal hidden aspects of their growth processes. Firstly, I implemented and benchmarked two competing segmentation algorithms to process raw SEM images and localize surface regions corresponding to the substrate, 1ML, and 2ML. The first algorithm employs a statistical approach, named global thresholding, while the second is based on supervised machine Learning. These two algorithms were evaluated on a batch of wafers where tungsten disulfide (WS₂) material was grown, reaching a maximum of 2ML. The machine learning algorithm demonstrated exceptional performance, achieving segmentation success rates that surpassed 98%, outperforming the global thresholding technique, which has a success rate of 86.5%. Subsequently, other algorithms were developed to extract quality indicators of 2D material layers from the segmented images, such as the coverage rate, and the count of basic crystals and islands. Reviewing all extracted properties enabled us to assess the process uniformity on wafers across different facets. On the other hand, the cross-analysis of these features unveiled some fundamental properties of the studied growth process. We determined the 1ML coverage at which crystals transition from a quasi-isolated growth to the coalescence phase, as well as when the formation of a uniform 1ML begins. Finally, we deduced the important relationship between the growth rates of 1ML and 2ML.

As the semiconductor structures become increasingly miniaturized and complex, the process of measuring and analyzing the structure using a microscope becomes crucial. High-resolution transmission electron microscope (TEM) images are widely used, but they are expensive to acquire and analyze. If the region and boundary of the material in the TEM image can be automatically segmented, the measurement cost will be reduced. We proposed a method to generate a segmentation label for a TEM image using a deep learning model that performs segmentation based on weak supervision and active learning. The proposed method achieved an accuracy of 98% in 10% of the time compared to the manual method. This approach will reduce the cost of high-resolution TEM image analysis and accelerate the semiconductor device development process.

Next-generation space telescopes under development by NASA will require high efficiency and resolving power soft x-ray spectrometers which can provide an order of magnitude increased performance compared to present space instrumentation. For the past decade the MIT Space Nanotechnology Lab has developed new x-ray spectrometer concepts based on so-called critical-angle transmission (CAT) gratings which exploit the principle of efficient x-ray reflection below the critical angle for total external reflection. These devices require challenging high-aspect ratio (HAR) “nano mirror” grating patterns with well controlled bar tilt angle and sub-nm surface smoothness. Gratings are patterned with precision (110) SOI wafers using 193 nm lithography and etched using a Bosch process. In this paper we present the first results of applying Mueller Matrix OCD mapping to our silicon HAR device geometry and compare with small angle x-ray scattering results.

The paradigm shift to extreme ultraviolet (EUV) lithography for circuits with sub-10 nm nodes brought about ultrahigh-precision optics and masks in reflective optical paths, creating challenges in the fabrication and metrology of the elements. The reflective optics and masks and ultrafine reticles on wafers offer the impetus of new complimentary CD metrology techniques that offer high-resolution dimensional probes in reflection geometry. In this work, we developed reflective hard X-ray holography imaging as the next-generation metrology tool for EUVL wafers/optics and wafers, without any sample modifications (milling and thinning). We demonstrate the capability of a new surface-reflection-based X-ray holography method for determining 3D dimensions of planar surface patterns supported by simple (but thick) substrates with nanometer resolutions. We anticipate that the holographic imaging technique will immediately benefit the nondestructive CD metrology of EUV reflective optics, masks, and reticles on wafers.

As the manufacturing process is more integrated, in the field of metrology, there is an increasing demand for method to monitor local dispersion of measurement value that can trace randomly generated week points in the chip. Since it is difficult to obtain local dispersion with an optical method where the relatively large spot compared to the size of the target structure, many attempts have been made to use other method such as scanning electron microscopy (SEM). It is clear that SEM is suitable for obtaining local dispersion thanks to its high resolution, but it is difficult to obtain thickness information because only contrast data is included in the image. From these demands, a method using gray level (GL) index of the SEM image to estimate the depth of the target pattern has been proposed. However, because it is an index that simply correlates the GL value to the depth without considering pattern geometry, it follows different trends depending on the design rule and dispersion of the critical dimension (CD) and depth. In order to overcome this inhomogeneity of the GL index, in this study, we propose 3D GL index considering the field of view (FOV) of secondary electron (SE) emission according to the 3D geometry of the pattern. We apply effective FOV derived from SE emission function estimated by Lambertian distribution and CD and depth of the pattern to conventional GL index. As a result of applying it to the polysilicon hole pattern and comparing it with the vertical-SEM depth measurement, unlike the existing index, 3D GL index shows a clear linear trend with high correlation R2 of 0.781 regardless of design rule and dimension variation. In that it can more accurately and robustly respond to process variation, the proposed 3D GL index can increase the utilization of the depth monitoring method using SEM image.

The accurate measurement of the thickness profile, particularly in the presence of non-uniform thin films deposited on substrates with warpage, is a crucial aspect of various applications spatially, in the overlay process of the semiconductor industry. The conventional method of Fizeau interferometer-based shape and geometry measurement has limitations in nanometer-level accurate volumetric profile measurement when non-uniform and complex thin films are deposited upon a warped Si substrate. Spectroscopic ellipsometry can be the best candidate for ultra-thin film volumetric thickness profile metrology rather than spectral reflectometry. But current spectral ellipsometry is time consuming. To address these challenges, our research group has made significant advancements in the field of spectroscopic imaging ellipsometry by developing dynamic spectroscopic imaging ellipsometry (DSIE). In this study, we describe a dynamic ultra-thin film thickness line-profile measurement method by adding a Mach-Zehnder interferometer module to a dynamic spectroscopic imaging ellipsometer. The proposed system can provide nanometer-level ultra-thin film thickness line-profile and the warped surface profile information of a Si substrate simultaneously.

We present recent experiments conducted with our tabletop EUV reflectometer to characterize the detailed geometry, composition, and topography of several nanostructured, polymer-based samples. The EUV measurements are performed without sample damage or any significant sample preparation. Correlative STEM measurements confirm the EUV results, but require extensive sample preparation.

As scaling in semiconductor devices continues, the aspect ratios of deep trench isolation (DTI) structures have increased. DTI structures are used in power devices, power management ICs and image sensors as a method to isolate active devices by reducing crosstalk, parasitic capacitance, latch-up and allowing for an increase breakdown voltage of active devices. Measurement of these structures in high volume manufacturing (HVM), with non-destructive technology, has mostly been limited to the depth and top width of the DTI structure, while the bottom width (BCD) has not been able to be reliably measured. Here we present two different optical metrologies, “conventional” OCD and IRCD, that operate in the UV-VIS-NIR and MIR region of the electromagnetic spectrum, respectively, and discuss the measurability of DTI sidewall profile, bottom width, and depth in BCD (Bipolar CMOS DMOS) power management IC devices for each method at various pitches and line to space ratios. Experimental data will be presented showing sensitivity and discrimination of IRCD to a DOE specifically on the bottom width for three different structures.

For many years, e-beam SEM metrology has been quite conservative. However, a few years ago, we began to observe a sort of restlessness in the field, a trend that was consistently confirmed year after year since then. Such a change was mainly driven by the daunting specification requirements for the advanced metrology nodes and High Numerical Aperture Extreme Ultraviolet Lithography (High NA EUVL), as well as by the device evolution in terms of architecture. We observed a systematic attempt to expand the application space in which the e-beam SEM had operated, tackling issues ranging from metrology of 3D structures to edge placement error, voltage contrast, e-beam inspection, and more. Such an expansion of the application space has forced heavily automated SEM to evolve into something different: a more flexible and powerful e-beam tool focusing not only on CD metrology, but on a range of novel use cases. To implement these new applications, it soon became evident that it was necessary to expand the range and type of tool specifications and features. We observed changes in landing energy, beam current, resolution, as well as algorithms. The detection process changed too, and higher current and better detection efficiency opened the door to a variety of back-scattered electron applications. Artificial intelligence is now critical not only in terms of speed of analysis, but most importantly for the quality of its results. Multibeam tools are fast approaching and have the potential to become a central technology element in the high-NA EUVL environment, where resolution and throughput for inspection must go hand-in-hand. In this paper, we provide an overview of the recent trends in e-beam metrology and inspection.

OPC (optical proximity correction) is a well-known and widely used RET (resolution enhancement technique) in optical lithography, which main purpose is improving pattern fidelity and process window. OPC relies on CD-SEM (critical dimension scanning electron microscope) images as a source of information for EPE (edge placement error) measurement, as input for the OPC modeling flow. However, as the pitch scales, stricter OPC modeling specifications, reduced metrology error budget, and increasing pattern complexities, create challenges for traditional CD-SEM metrology. Also, parameters like materials, landing energy and other scanning conditions, may have a different impact in the final image in terms of shrinkage, charging and distortion. All these effects need to be characterized during the modeling step to optimize OPC. Examples of EPE uniformity and pattern shrinkage are illustrated in Figure 1, for different scan conditions. With the increasing adoption of EUV (extreme ultraviolet) technology in the field of patterning and the upcoming introduction of High-NA (high numerical aperture) EUV, the need for further understanding of the EUV resist material interaction with a CD-SEM electron beam is also increasing. Low landing energy scanning approach is a way to minimize EUV resist damage during image acquisition and provide a more accurate view of EUV lithography effects. Also, to improve the design space coverage, resist (or lithographic) and etch modeling require thousands of measurements over different types of structures. Additionally, massive EPE statistics makes model building more robust. A contour may provide the equivalent of hundreds of different measurements – using the entirety of the contour instead of only relying on the placement of gauges, as in conventional measurement, further increases the sampling and the coverage of the produced model, which make contours the suitable choice. The influence of low landing energy is expected to be seen in the etch modeling step, where it should have higher accuracy and lower etch bias when compared to litho SEM data. However, a drawback of using low landing energy for image acquisition is a lower SNR (Signal-to-Noise ratio) compared to standard imaging conditions. This may represent extra challenges to the contour extraction algorithm which needs to be robust. These challenges can be addressed by using a model-based approach. In this work, different CD-SEM scanning conditions were studied in order to find optimal working points for modeling purposes. Since different patterns have varied outcomes under different e-beam conditions, thus affecting the model residues, more than 600 distinct patterns from EUV lithography – going from 1D to complex 2D – were selected to provide enough sensitivity to when building the litho and the etch models. Contour metrology is used to detect the edges, for EPE analysis, and to provide inputs for the modeling flow. At last, one of the key aspects of this work is the use of low landing energy (150eV) scan approach to minimize the resist shrinkage effect, while accounting for resist charging in the modeling. All these factors will provide further insight and optimization into this new era of metrology.

The adoption of EUV technology in DRAM fabrication is primarily driven by the pursuit of higher device densities, improved performance, and increased energy efficiency. EUV's shorter wavelength (13.5 nm) enables enhanced resolution and finer patterning, enabling the production of smaller memory cells with reduced feature sizes. As the target patterning size is becoming sub-10nm, line edge/width roughness (LER/LWR) is the centerpiece in controlling uniformity of pattern going through the lithography process. Accordingly, it is essential to figure out the dedicated CDSEM metrology method for EUV step without any image quality degradation, charging issue, and e-beam damage that can hinder accurate diagnosis of the real process status. Empirically, it is highly difficult to predict the best metrology condition that fits to the specific resist material, dimension, and geometry due to complex stochastic effect caused by secondary electron inside photoresist (PR) material. Here we represent experimental results of PR damage caused by electron beam irradiation with different landing energy for both line and space (LS) pattern and contact hole (CH) pattern. The results enabled us to define the effect of the landing energy and geometry of pattern on the critical dimension (CD) and roughness. We examined electron irradiation induced damage by comparing etch bias of fresh location and e-beam exposed location on etch process step to fully understand shrinkage and deformation behavior. For the roughness measurement of CH pattern, we adopted new metric which enables us to quantify contact edge roughness and shape of contact. Utilizing various metrics, it was possible to observe damage on the process, which was not observed only by CD changes, and it was confirmed that the primary beam with low landing energy could be used to not only reduce damage but also enhance surface sensitivity of metrology without bias which is crucial for stochastic effect monitoring on the EUV process.

In device overlay is an important contributor to the on-product overlay budget. Well known are overlay bias effects, i.e., differences between overlay targets and in-product features. These can be corrected by a non-zero overlay correction in the run-to-run system. In this paper, we examine micro-scale effects, which happen on scales of a few micrometers, for which there is not exposure tool correction possible. With a high-voltage SEM, we use a novel method to investigate both logic and memory wafers and identify several micro-scale effects that are a significant contributor to the on-product overlay budget. We characterize the behavior across the wafer and local variations. In the root cause analysis, we find several possible explanations including mask writer issues, local stress, and impact of the product pitch.

Technology nodes shrink leads to a very tight process control window. As an inline metrology tool, CD-SEM (Critical Dimension Scanning Electron Microscope) matching error for the entire fleet should be less than 10% of the process control window. The tight matching is also obligated to be coupled with HVM (High-Volume Manufacturing) requirements of high tool availability and fast recipe creation. To meet these challenging restrictions, iterative improvements on existing methodologies are no longer sufficient and a complimentary approach needs to be adopted. The operation of any fab tool, and specifically CD-SEM holds an enormous amount of information. The tool’s various modules parameters such as: currents and voltages and environmental status (temperature, noise etc.), the working point and beam parameters: scan rate, beam current, pixel size, landing energy, beam shape and size, etc., and the specific wafer characteristics: materials, pattern, charging effects etc. Encapsulating all these together contributes to the final matching error sensitivity. As we are moving towards a data-driven era, this information can be utilized to better predict, correct, and improve matching (i.e., by neural network, machine learning etc.). Furthermore, today’s matching metrics, which are based on 1-D CD measurements from SEM images (a convolution of the final SEM image and algorithm), are indirect and are not sufficient for understanding the whole story. In this paper, we propose a complementary approach that combines iterative improvements with data-driven methodologies that can enable a matching level suitable for EUV requirements in the Å era.

Background: Process window metrology is used in manufacturing to determine best dose and focus for the scanner, but current metrology uses defect inspection to determine best focus and thus is expensive and time consuming. Aim: Ideally, an alternate stochastics metric (such as linewidth roughness for line/space patterns) could be used as a substitute for defectivity measurements, saving time and money. Approach: Here, the Probabilistic Process Window (PPW) is evaluated as an improved alternative to the plan of record approach, where only CD-SEM images are collected and evaluated. Results: The PPW was found to provide results that matched to the plan of record approach, but with increased rigor and improved precision. Conclusions: As a result, critical layers on future DRAM manufacturing nodes will use the PPW for best dose/focus scanner control.

We have developed a high-resolution x-ray microscope with spatial resolution better than 100 nm. The utilized x-ray energy of the microscope is 17.5 keV that can penetrate through standard silicon substrate and enables to observe embedded nanoscale metal structure and defects, nondestructively. We have applied the present x-ray microscope for investigating 3D flash memory devices and observed precise metal filling structure in there. In addition, defects in the circuit area were also found.

In the manufacturing of CMOS devices, the golden standard for determining yield at various stages of production is electrical testing. This allows for the identification of failing devices or early yield failures before proceeding to subsequent steps. However, the failure of electrical tests can occur due to various reasons inherent to the structures of the devices. Additionally, a comprehensive analysis is necessary to ascertain the root cause of the failure mechanism once a device does not pass the electrical tests.

On-product overlay (OPO) is a critical inline process control parameter in semiconductor manufacturing. One of the main factors that induce the overlay error is non-lithography processes like etching, deposition and cleaning. The overlay margin is getting tighter as the device technology advances and detecting the root cause of process-induced overlay error is a main problem to improving the OPO. However, it is not an easy problem to solve due to the lack of inline monitoring data on non-lithography processes. Even if we evaluate inline monitoring data, it is too sparse to do in-depth analysis compared to abundant lithographic overlay data. Instead, we can make use of data from the PWG patterned wafer geometry metrology system, which can measure high-density data with high throughput. In this paper, we introduce a comprehensive method of detecting the root cause of the process-induced overlay errors based on inline PWG data. Our target device is a 3D NAND product with process-induced overlay errors due to wafer geometry. We start our analysis by tracing PWG GEN3 data for the same wafer in a wide process step range. We compare the GEN3 signature to an overlay error signature of a target lithography layer to filter out suspicious processes. From the suspicious processes, we derived optimized KPIs that discriminate between good and bad wafers in terms of process-induced overlay errors, which are then used as a monitoring metric. With the optimized KPIs, we discern which process is the root cause of process-induced overlay errors to help drive corrective actions and improve OPO on the target device. Finally, we propose a comprehensive framework that is not limited to PWG data but applies to other available inline data such as alignment, ADI and AEI overlay and NZO.

As semiconductor process technology needs to be advanced, the difficulty of patterning increases and unexpected pattern defects occur. In fact, it is very important to quickly identify and resolve these pattern defects in advance, but there is a limit to measuring all of these pattern defects that occur in wafers. In particular, in order to overcome metrological limitations, it may be best to extract actual potential pattern defects by classifying various types of patterns that actually exist. We measured how to classify weak patterns by sampling them based on previously known weak pattern group libraries, simulation-based weak patterns, and unique patterns. Through this method, engineers can subjectively judge how to find weak patterns, and it can be difficult because there is a possibility that the probability of weak patterns is low depending on the limited measurement capacity. In this paper, unsupervised learning is used to cluster and classify by pattern type based on the various features of pattern. Then, based on reliable wafer data for various classified pattern types, the degree of vulnerability to defect was quantified for each classified cluster to give a ranking for extracting a weak pattern group for each cluster, and the weak pattern was extracted based on this to confirm a high weak pattern detection rate. In addition, it provides effective solutions to extract weak patterns from various databases (DBs) and specifically to give reliability to visualization methods.

Si/SiGe heterostructures are gaining traction as a starting template in applications such as Gate-All-Around Field-Effect Transistor (GAAFET), complementary FET (CFET), and 3-dimensional dynamic random access memory (3D-DRAM), where the SiGe alloy plays the role of sacrificial material for channel release. However, the formation of crystalline defects (e.g. crosshatch) in the epitaxially grown layers plays a critical part in determining the overall device performance. As such, it is key to be able to control the defectivity level using large surface area inspection techniques. The challenge of such inspection is that it must combine a high enough throughput to detect low-density defects together with sensitivity to nanometer size defects. In addition, the technique should also be able to distinguish these elongated one-dimensional crystalline defects from other types of defects. In this study, we investigate the impact of the number of Si/SiGe bilayers on the crystal defect distribution utilizing a combined approach of optical inspection and extensive e-beam review for both qualitative and quantitative defect characterization. In-line optical inspection techniques revealed that the crosshatch density and distribution varied significantly with the number of Si/SiGe bilayers. These observations were then confirmed by high-resolution e-beam review coupled with image analysis and signal processing to enable crosshatch quantification. Our approach considers an initial investigation on thin Si/SiGe bilayers (up to ~5x bilayers) and is further extended to thick stacks (up to 60x bilayers) to evaluate the capability of optical inspection as the high-throughput reference technique. In conclusion, this study aims to develop a methodology to investigate the crosshatch density in Si/SiGe superlattices, using optical inspection and e-beam review as main characterization tools. These techniques offer valuable insights in terms of defect distribution at the wafer level for the design and fabrication of next-generation semiconductor devices.

Subsurface structures exhibit contrast in the backscattered electron (BSE) signal of a scanning electron microscope (SEM) if they and the surrounding material have different BSE yields and the electrons are energetic enough to make the round trip. Gate-All-Around (GAA) transistors have gates formed by multiple subsurface nanowires or nanosheets. I will present Monte Carlo simulated BSE images of a virtual GAA transistor viewed from different angles. Simulations quantify the increase of resolution and decrease of contrast with increasing beam energy. They can inform the choice of operating conditions and the assignment of image features to their corresponding structures.

As CMOS node advanced, device patterns become smaller and denser, which as a result, decrease overlay budget. Each contributor to overlay error is significant and should be minimized, even at early stage of technology development. The performance of optical overlay metrology is challenged by the difference between optical target and device structure, which response differently to lithography optics (aberration response), hence reduce correlation to device overlay. E-Beam overlay can mitigate this gap as it can measure device-size structures. In this case, the challenge is to measure small, dense and buried patterns, which may have low visibility (contrast and edge resolution), but still provide acceptable total measurement uncertainty (TMU) to reduce error budget from the tight overlay specs. Finding optimal target where its design is similar or close to device and is measurable with robust performance, without designing and re-design targets in multiple tape-out cycles, can be done by simulating scanning electron microscopy (SEM) measurements of different device-like targets and find the optimal point where predicted performances are good and the design is as close to the device. In this paper we propose a method that evaluates measurement performances of different SEM overlay target designs using e-Beam simulation of back-scatter electrons (BSE) yield from buried layers. Targets with different design rules: pitch, critical dimensions (CD) and edge-to-edge distance are simulated at different measurement conditions and results are compared to measurement of actual targets on wafer. The comparison shows that measurement performance can be predicted by simulation, which can point out optimal target design and measurement conditions.

Scanning Electron Microscopy (SEM) technology makes use of an electron beam (e-beam) with wide energy range from 0.1 to 50 keV, so it is possible to measure wafers from surface to deep and buried structures. Due to its superior accuracy, it is widely used for in-line metrology and inspection (MI) process. As devices scaling down for performance enhancement, the MI process became inaccurate due to the target structure shrinkage and complicated electrons’ behavior inside it. To overcome the challenges, accurate simulation tool is required to understand its underlying mechanism theoretically. In this paper, we propose a unifying framework for simulating SEM operation by implementing Nebula e-beam computing algorithm on the Technology Computer-Aided Design (TCAD) environment. The proposed framework integrates various physics models including the scattering and transport behaviors of electrons, which enables to calculate the important trajectories of electrons in the most important regions of wafers. In addition, it gives an expandability on further integration thanks to the computability of TCAD environment. We validate the proposed framework with demonstrating key applications on real products.

As semiconductor devices continue to introduce new materials and structures, not only the dimensions but the material properties are becoming important in determining the device properties. Properties of insulator films used in transistors and memory devices are of particular interest as they determine the characteristics as well as the reliability of the devices. The material properties can depend not only on their deposition conditions, but also on the processes they are later exposed to, such as annealing and etching. Therefore, the film properties can change over the course of device fabrication. To ensure efficient production of these devices, an inline tool for metrology and inspection of material properties is desirable. One way to evaluate the material properties is to measure the material’s response to application of voltage. For this purpose, we have developed a laser-assisted SEM, an SEM with laser irradiation capability to control the electrical state of the material under SEM observation. The laser is used to inject carriers into insulators to control or neutralize insulator charging caused by the electron beam. Therefore, the combination of an electron beam and laser irradiation can be used to control the sample voltage. The material response can be measured in either the amount or energy of the secondary electron signals. Therefore, how the signal changes depending on the electron beam or the laser condition can be used to indirectly evaluate the material properties of the sample. In this work, we have used the laser-assisted SEM to detect the change in material properties of insulator films under annealing and different etching plasma conditions. The laser-assisted SEM was found to be sensitive not only to bulk film properties, but also to buried interfaces. These new features can make the laser-assisted SEM useful as needs continue to grow for inline metrology and inspection of semiconductor devices.

Contamination in electron microscopy is a persistent problem. Depending on the kind and amount of precursor molecules, vacuum level, sample material and temperature, and the intensity and energy of the irradiating electrons, deposition can overwhelm removal, or vice versa. Electron irradiation with 100 eV electrons is a new method for achieving ultra-high cleanliness (UHC), so the sample can be irradiated by electrons indefinitely without depositing any perceptible amount of contamination. The simple and effective, high-vacuum cleaning method creates new possibilities in many electron- and ion-based measurements where UHC is needed, but ultra-high vacuum is not necessarily required.

Advanced packaging enables the heterogeneous integration of different components, to integrate functional devices needed for the ever-diversifying needs of compute market. For advanced packaging to achieve a high level of integration, the package substrate must be densely populated with various components, often in a complex 2.5D or 3D configuration. This requires extremely fine pitch interconnects and high accuracy alignment between different components. System-in-package use multiple lithography steps to print the redistribution layers connecting the chips (RDLs), driving an increasing need in alignment and overlay metrology. Another limitation of conventional reticle driven lithography is that scaling is limited by die placement accuracy and warpage caused by the stacking of multiple chiplets and substrates. To address these limits in productivity and scaling, digital lithography for advanced packaging was introduced, to print the RDLs in the needed rotation to stich the interconnects to the packaged devices. To avoid cracking, delamination and voids, tighter inspection specs are needed. And to achieve high performing integrated system-in-package, new test steps are required to match chiplets in performance way ahead before sort, but the increasing I/O density requires contactless test as conventional probes become too large and cause defects as they perform test. In this talk we will cover the Heterogenous Integration processes that drive the need to form an ecosystems of metrology inspection and test to fuel Moore’s law via high performance system-in-package

Wafer-to-wafer hybrid bonding is a key technology for achieving high-density three-dimensional interconnections in semiconductor devices. This technology directly bonds Cu pads formed on the surface of two wafers, where the surface height of the Cu pad compared to the SiCN surrounding the Cu pad have to be within a few nm. We have developed a method to measure the Cu pad surface height with sub-nm precision by using a top-view scanning electron microscope image. The proposed method is based on the physical principle that the difference in the backscattered electron (BSE) signals of the opposing detectors is dependent on the slope. It estimates the slope of the target with the BSE signal and then calculates the height of the target on the basis of this slope. We compared the Cu pad height measurement results by this method with those by atomic force microscopy and found that ours provided measurement precision on the sub-nm order and demonstrated the capability for evaluation of layout dependency and intra-wafer distribution. Because of its speed and alignment capability, our proposed method is promising for Cu height control in wafer-to-wafer hybrid bonding.

Comprehensive through-silicon-via (TSV) characterization, including grind side measurements, is critical to ensure device reliability in chiplet technology. Here we report on TSV metrology using spectral interferometry (SI), which is used to acquire absolute phase information of polarized and broad-band light interacting with a sample. This phase information can be translated into the optical path length of the partial beams traveling within the structure. We utilize the spatial separation of peaks related to light reflected from the top surface and the surface of interest to directly measure the TSV depth after reactive ion etching as well as the reveal height on the grind side, without modeling and even in the presence of multilayers or surrounding patterning. Polarization-dependent SI measurements enable the quantification of asymmetry at the bottom of the TSVs not visible in top-down CD measurements. SI is robust and fast and unveils novel information in TSV metrology not accessible with established in-line metrology techniques.

In the past few decades, leading edge logic technology scaling has been the main driver for semiconductor metrology developments. As traditional device scaling is slowing down, the semiconductor industry is focusing also on heterogeneous integration approaches, which leverage advanced packaging technologies to integrate devices designed and manufactured separately using the most suitable process technology for each device. Heterogeneous integration presents significant metrology challenges, which are different from what is encountered at the logic device level in terms of materials and specifically dimensions. Large-scale 3D structures need to be characterized with unprecedented accuracies and advanced optical techniques play a pivotal role. In this paper, some metrology challenges in heterogeneous integration are introduced and discussed related to TSV characterization including depth and reveal height, wafer bonding measurements, and dimensional and overlay metrology for processing leading to bump receivers and bump formation. Current capabilities utilizing various imaging and interferometry techniques are presented and their limitations discussed.

3D heterogeneous integration is an evolving segment in integrated circuit development and advanced packaging to drive More than Moore (MtM) chip scaling. Heterogeneous integration allows IC manufacturers to stack and integrate more silicon devices in a single package, increasing the transistor density and product performance. Product designers seek higher bandwidth, increased power, improved signal integrity, more flexible designs (mix/match different chip functions, sizes, and technology nodes), and lower overall costs. The 3D heterogeneous integration roadmap shows a decrease in the bonding bumps/pads pitch to a sub-micrometer level, enabling a higher bump I/O density. Key process development activity is occurring in the wafer-to-wafer (W2W) bonding process to reduce interconnect pitch to small values. In the W2W process, a wafer bonder is used to align and bond two whole wafers. To successfully unite these two bond surfaces with a very small pitch, tight control of the bond pad alignment is required to ensure the copper pads line up properly before being bonded, driving an increased need for overlay metrology precision and die-bonder control. The bonded wafers are subsequently cut up into stacked chips using a dicing process and then undergo testing and further packaging. Advanced processing control (APC) for W2W hybrid bonding is an important factor in fulfilling the target on-product overlay (OPO) via litho inputs, in-plane distortion (IPD), overlay (OVL) and bonder correction knobs. This work will evaluate the various aspects impacting OPO, including the pre and post-bonding error budget.

In this work, we study the optical overlay metrology performance and impact of an integrated hard mask etch step using the dry resist process with High Numerical Aperture Extreme Ultraviolet Lithography (High NA EUVL)-related thicknesses. Diffraction-based overlay measurements were performed after dry development and integrated hard mask etching for different overlay target designs. The measurement precision for the after-dry development measurement is shown, and the benefits of using integrated hard mask etch overlay metrology with respect to after-dry development are discussed.

We have demonstrated the unique capabilities of spectral interferometry (SI) with vertical traveling scatterometry algorithms (VTS) to solve 3D NAND challenges by measuring complex layer thicknesses of the multideck 3D structures directly from the VTS signals, without modeling, with Cell Over Periphery (COP) underlayer filtering. Multiple examples are presented in the paper, including the measurement of the thin and thick layers of memory structures above the complex logic arrays and the remaining thickness of the fully processed Si wafer from the back side after thinning. In addition, VTS and AI enable direct profiling of the deep through-type cell metal contacts in the areas with nonperiodic staircases and significant lateral variations under the measurement spot.

Scanning electron microscope (SEM) imaging is widely used in semiconductor manufacturing, including for defect inspection. One use is to identify contact holes that are potentially scummed (not completely cleared to the substrate). However, the visibility of the bottom of a contact hole (and thus the ability to identify scumming) is limited when the aspect ratio of the hole becomes high. In this work, a large designed experiment simulation study using AMAG SimuSEM will thoroughly explore the parametric influences of profile and CD for via bottom detection in the secondary electron regime, including not only aspect ratio, but also influences of sidewall angle and footing, along with defect cases of incomplete etch or resist residues in hole bottoms. We will show the expected trends to the signal evolution as a function of the applied perturbations, and demonstrate that simulation can be used to understand and estimate the thresholds for detecting via footing and scumming.

Scanning electron microscopy (SEM) is generally used for line edge roughness (LER) measurement; however, it is difficult to achieve high precision LER measurement of photoresist due to shrinkage caused by electron-beam (EB) exposure. We have developed a metrological tilting-atomic force microscopy (AFM), which has a tip-tilting mechanism to measure vertical sidewall. In the last conference, SPIE-AL-2023, we demonstrated quantitative evaluation of shrinkage of ArF photoresist due to EB exposure by measuring the pattern before and after EB exposure [Kizu et al., Proc. SPIE 12496, 1249605 (2023)]. In this study, we will demonstrate quantitative evaluation of shrinkage of EUV photoresist due to EB exposure by the AFM technology.

Sub-2nm On Product Overlay (OPO), scribe line width reduction, and high-order scanner correctibles are driving innovative overlay (OVL) targets. One promising new imaging-based overlay (IBO) OVL target to address such challenging trends in multiple semiconductor segments is a small pitch AIM (sAIM). sAIM is in essence an IBO target with grating (previous layer) beside grating (current layer) which could be placed in a few layouts: square, rectangular, and Mosaic. In this work, we will present the sAIM operational concept and performance including Total Measurement Uncertainty (TMU), residuals, and accuracy (ADI on-target offset vs. ACI on-device or target), which is often referred to as Non-Zero Offset (NZO).

The qubit count of superconducting transmon-based quantum processors is steadily increasing. Some processors are already beyond the 100-qubit scale. In order to keep the development cadence of those quantum processors high, the test time per qubit needs to be strongly reduced from days to hours. Here we present a test time study based on extracting a single-qubit fidelity using a randomized benchmarking protocol. We show that more than a dozen other tune-up steps are required before a randomized benchmarking protocol can be executed on a qubit. En bloc, such a structured workflow leads to a test-time of about 20 mins per qubit. By extrapolating, we find that testing single-qubit fidelities on a hecto-qubit scale quantum chip using the randomized benchmarking protocol would take about 2.5 days. Executing the test protocol is furthermore embedded in a total test cycle that takes into account that a chip needs to be inserted, tested, and retrieved from the system, consisting of a cooldown to 20 mK base temperature and afterwards a warmup to ambient conditions. The whole process of chip testing, starting with insertion and ending with the retrieval of the quantum processor under test is estimated to take about a week. Considering the current state of technology, such a cadence in chip testing can be considered high throughput.

In traditional semiconductor packaging, manual defect review after automated optical inspection (AOI) is an arduous task for operators and engineers, involving review of both good and bad die. It is hard to avoid human errors when reviewing millions of defect images every day, and as a result, underkill or overkill of die can occur. Automatic defect classification (ADC) can reduce the number of defect images that need to be reviewed by operators. The ADC process can also be integrated with AOI engines to reduce nuisance defect images to reduce AOI image capturing time. This paper will focus on how to utilize Onto Innovation’s TrueADC software product to build ADC classifiers using a multi-engine (ME) solution. The software supports CNN, DNN and KNN algorithms. The use of CNN and DNN are currently mainstream in the development of deep learning (DL) for ADC classification in the semiconductor industry. We will address how to improve classification by using multiple models in the classification process with unique algorithms. As a result, the user can achieve industry requirements with very demanding specifications, like high accuracy, high purity, and high classification rate with very low escape rates.

In this work, the measurement of local variables such as Line Edge Roughness (LER) and Line Width Roughness (LWR) in large field of view (FoV) Scanning Electron Microscopic (SEM) images is demonstrated. We show that larger FoV images include more of the lower frequency components in the roughness profile and hence these variables are measured more accurately. We also show that larger FoV images provide a better statistics which improves the precision of the measurement significantly. We also address the impact of image distortion on LER as the main challenge of large FoVs. The study is performed on large FoV 8µm×8µm images with line/space features, acquired by massive metrology capability of a high throughput eP5 SEM. We crop the images to smaller ones and compare the results measured for different FoVs, with and without distortion correction. We see that by the distortion correction, especially in low frequency, we can calculate the local variables accurately.

Accompanying the microfabrication and the complexity of the semiconductor manufacturing process, measurement and inspection using a scanning electron microscope (SEM) have become increasingly important for semiconductor manufacturing. Therefore, we have introduced an image denoising algorithm based on supervised deep learning with measurements for model training that transform a low signal-to-noise ratio (S/N) SEM image into a high S/N one, thereby improving the measurement success rate and maintaining measurement precision. Our experimental results demonstrated its effectiveness by an algorithm for enhancing throughput. However, performance may degrade when dealing with images containing features not included in the training dataset because deep learning models generally rely on trained features. Therefore, we propose high throughput CD-SEM metrology using image denoising based on deep learning that include a technique to statistically monitor deviations from the training images during model operation. In this study, we mainly discuss about monitoring module. To verify effectiveness of our proposed monitoring module, we first acquired sets of normal images used for training a deep learning model and sets of deviated images in which the SEM imaging recipe was partially changed. Then, the distribution of statistical values for noise and brightness features in the normal image set was used as a reference to compare the deviated image sets by the proposed method. As a result, the detection rate of the deviated images achieves 100%, and the false detection rate achieve 0% by combining of multiple statistical value distributions. By detecting deviated images that may degrade measurement performance, it is possible to maintain measurement precision and operate high-throughput measurement by using a denoising model based on deep learning.

Scanning electron microscopes for semiconductor device inspection require high-throughput performance for full-wafer inspections. To achieve high-throughput inspections, we need to inspect a large field of view (FOV) with a high current. However, these inspection conditions cause the sample to experience electrical charging. This sample charging causes abnormal contrast and image distortions. In this paper, we show that the sample charging can be controlled by the irradiation current, and image distortion can also be minimized. We also show that the sample charging can be controlled by the voltage applied to the sample, and we explain the mechanism of charge formation.

As the design rules for semiconductor devices continue to shrink, layer-to-layer overlay of actual circuit patterns needs to be measured by using a critical dimension scanning electron microscope (CD-SEM). In addition to the overlay, process variations are making not only local size variations but also local position errors in patterns on the same layer increasingly non-negligible compared to pattern size. In cases where upper and lower patterns partially overlap, these variations and errors cause variations to occur in the positions and visible area of the lower layer patterns in SEM images. As a result, the center position of each lower layer pattern has become difficult to accurately measure resulting in errors in the overlay measurement. In response to this problem, we have developed a method for dynamically placing measurement area cursors for overlay metrology using segmentation technique. This method determines a measurement area cursor by recognizing the position and size of each lower layer pattern through segmentation images generated from the target SEM images using unsupervised deep learning. The performance of this method is evaluated by creating imitated images having the programmed overlay, the local size variations, and the local position errors. We compared the measurement results for the imitated images obtained by the proposed method and a conventional method that uses fixed measurement area cursors and found that the proposed method maintains sensitivity and repeatability even for targets where sensitivity and repeatability degrade with the conventional method due to process variations.

While extreme ultraviolet lithography has contributed to sub-10nm microfabrication, there are concerns about stochastic defects. Thus, the process evaluation requires fast and precise inspection of entire wafers. To do this, large field-of-view (FoV) e-beam inspection has been introduced. However, large FoV inspection sometimes suffers from image degradations due to aberrations and/or charged wafers that cause false detections during image comparison inspection. To reduce these false detections, we developed a deep learning-based image adaptation method to reduce the difference between the reference image and degraded inspection image. Here, the adapter that simply minimizes the difference often falls into over-adaptation that eliminates the difference in defect characteristics and decreases detection sensitivity. To address this, we introduced a patch-wise blind-spot network (PwBSN) that recognizes only the image degradation by leveraging the property that the defect region is smaller than the image degradation region. Since the PwBSN can only use surrounding regions due to its architectural constraints, it only minimizes the difference in degradations except for defects smaller than patches. We applied this method to deep learning-based die-to-database defect inspection. The evaluation on SEM images showed that the proposed method detects only defects, while a conventional method detects both defects and image degradation regions.

Deep learning models have been proven to automate metrology tasks. It provides accurate, robust and fast results if it is trained with proper data. Nonetheless, obtaining training data remains tedious. It requires an expert user to delimitate objects boundaries in several images representing tens to hundreds of objects. Instead of drawing precise boundaries, we propose a tool relying on a rectangular bounding box to detect and segment objects. For complex applications with non-homogeneous background, the user must draw one box per object to segment them. For more homogeneous objects such as contacts, one box on the whole image can successfully segment all objects at once. To further improve the capabilities of the tool, we provide the possibility to segment the different material regions inside the found objects. The process's robustness is demonstrated through benchmarking in two contexts. Firstly, we trained two Mask R-CNN models, one with manual segmentations and the other with segmentations obtained using our tool. We compared the two models to the manual reference and found that the tool is consistent with human annotations while reducing annotation time by a factor of 30. Additionally, the tool greatly reduces user bias as the selected segmentation features are more stable. Furthermore, we suggest extending the tool to identify objects within the already found objects.

In today’s advanced semiconductor industry with the multitude of new products and device requirements, lithography process changes are inevitable and expected due to tighter overlay specifications and the increasing influence of process effects. To minimize the overlay impact from the wafer-to-wafer and lot-to-lot variation, lithography engineers often need to adjust wafer alignment and overlay strategies to optimize product yield. Overlay simulation methods are often used to estimate if new alignment and/or overlay strategies can help achieve better overlay performance. By removing the old corrections from the original alignment and overlay data, and then applying new corrections, the overlay performance can be readily predicted, saving significant time. However, available software suites only simulate the current layer overlay. Overlay risks would therefore remain on subsequent layers without an effective simulation method to predict the impact resulting from changes to the alignment and/or overlay strategies on the current layer. In our study, we demonstrate a new method to simulate the overlay performance on the subsequent layers by re-calculating the current layer exposure grid. Our dataset has 3 layers: L0, L1, and L2. On L1 (current layer), we apply a new alignment model and overlay control strategy with a feedforward solution. Then, we re-calculate the exposure grid to generate a new (virtual) alignment and overlay dataset for L2 (following layer). Finally, we estimate the overlay impact on L2 with the new alignment and overlay dataset and summarize the benefits of this new cross-layer overlay simulation method.

Nikon has developed a state-of-the-art wafer topography sensor dubbed S-meter-Z, which is based on an optical spectroscopy and novel correction function based on an optical model. The measurement repeatability is roughly 10 nm and has the potential to reach down to a few nm with additional improvements. Processed wafers with lithography patterns often have a complicated surface film structure, which induces the amplitude change and phase shift of the reflected light. This phase shift often causes errors in wafer topography measurement. The S-meter-Z minimizes these errors and provides accurate wafer geometry data for wafer process monitoring, which is essential for manufacturing today’s leading-edge microchip devices.

The semiconductor foundry industry struggles with challenges in high-product-mix manufacturing, necessitating enhanced flexibility to address diverse customer demands. Coordinating multiple chambers and process steps with varying designs and technology nodes poses complexities leading to reduced yields and increased costs. The chemical vapor deposition (CVD) process introduces thickness variations due to device layout design and chamber condition drift, impacting transistor parameters and yield. Managing chamber-by-chamber variations is critical for high-volume manufacturing, yet traditional solutions fall short in fab line management, resulting in throughput loss. Conventional VM relies on data from the process chamber, referred to as fault detection and classification (FDC), to predict metrology results. In this study, the extraction of design features for better predictive purposes across diverse layouts and technologies are highlighted. Siemens' Calibre® software is employed for design feature extraction, and machine learning (ML) methodologies to construct the extended VM model. An advanced process control (APC) system using the extended VM model for run-to-run (R2R) control is proposed. It incorporates design features, FDC, and measurements to achieve the desired thickness target. The system triggers updates to the extended VM model based on prediction errors. Through control simulations, the APC system significantly enhances process capability and reduces film thickness variations, confirming its effectiveness in a high-mix product foundry fab. Responding to the growing demand for custom-designed products, this paper suggests integrating an ML-based extended VM model with design features and FDC into the APC system, presenting a promise solution for high-product-mix manufacturing.

Overlay control continues to be a critical aspect of successful semiconductor lithography processing, with overlay control systems becoming more and more elaborate to meet the requirements of advanced semiconductor nodes. Sampling optimization is especially important including the number of overlay measurements to perform on each wafer, the number of wafers to measure per lot, and where exactly to measure on each wafer. Conventional sampling optimization methodology is to collect dense data for a short period and use this data to optimize the locations to measure on the wafer. In recent years, rule-based sampling was introduced to relax this data requirement and improve the time to result. However, in both scenarios, one single sample plan is generated in offline optimization, which is then used in high volume manufacturing (HVM) without change, hence named “static sampling”. In this paper, we introduce a “dynamic sampling” approach, where multiple rule-based sample plans are generated, that complement each other by measuring different locations on the wafer, while meeting spatial and population balancing criteria. These sample plans can then be used in an alternating manner on a per-wafer basis (wafer-by-wafer dynamic sampling) and per-lot basis (lot-by-lot dynamic sampling) in HVM. In this paper, we first demonstrate the risks and the inherent trade-offs associated with static sampling by using overlay budget breakdown and best/worst case advanced process control (APC) simulations. We then characterize the overlay control improvement potential of dynamic sampling schemes through APC simulations using multiple metrics: on-product overlay, rework overlay and monitoring accuracy. Finally, we calculate the on-product overlay versus throughput cost function analysis and determine which dynamic sampling scheme is the most useful for which throughput conditions.

Since the rise of transistors and integrated circuits, the semiconductor industry has seen rapid advancements, leading to today's microchips containing hundreds of millions of transistors. A pressing challenge in this industry is the emergence of defects, termed "hotspots," during the manufacturing process, affecting chip performance and reliability. In this study, we introduce a deep learning model that predicts hotspots during the design stage. To predict hotspot, our proposed framework generates Scanning Electron Microscopy (SEM) images from layout by combining segmentation and image-translation network. This model outperformed existing baseline models when tested on real industrial datasets, promising to refine the semiconductor design workflow.

Scanning electron microscopy (SEM) is used for metrology and inspection in semiconductor manufacturing. In addition, electrical defects such as short circuits and unintentional insulation appear as contrast differences called voltage contrast (VC) in SEM under low acceleration voltage conditions. Moreover, by using pulsed electron beams from a photocathode, the probe current can be arbitrarily changed by pixel in the SEM image. Using this technology, we succeeded in observing the change in the VC of the drain in the metal-oxide-semiconductor field effect transistor (MOSFET) by changing in electron beam irradiation on the gate only. In this study, to estimate the threshold voltage of n-type MOSFET (nMOS) from VC, we investigated quantitative changes in the specimen current of the drain (I_d) and the gate (I_g) due to gate e-beam irradiation ON/OFF during SEM imaging. The landing energy of the electron beam was set to 0.8 keV, the probe current was 6.3 pA, and the e-beam was irradiated onto only the gate and drain electrodes. I_d and I_g, which showed a positive value at the beginning, decreased with time, and saturated at negative values. When the electron beam irradiation to the gate was turned OFF, the I_d decreased further and reached saturation. When the gate e-beam irradiation was turned ON again, I_g recovered to a positive and then saturated again to a negative value. On the other hand, the drain Id increased when the gate irradiation was turned ON and returned to the same value as before it was turned OFF.

With the increasing complexity of semiconductor manufacturing processes and high overlay accuracy requirements, it is increasingly necessary to measure wafer characteristics accurately. When wafer distortion in shape and mark quality changes occur due to wafer characteristic changes, the measurement accuracy in overlay and wafer alignment decreases, resulting in lower yields. Canon has released the stand-alone wafer metrology tool (MS-001) as a solution for high accuracy wafer measurement. It has been reported that high productivity and overlay accuracy can be achieved by measuring the wafer distortion and exposing the wafer aligned based on the measurement results in the exposure system. In this report, the feasibility of detecting the mark quality changes, which is one of the factors of low measurement accuracy, was verified using product wafers. Moreover, it was demonstrated that MS-001 was successful in detecting wafer process variations with high accuracy. These results indicate that MS-001 can solve the issues caused by complex semiconductor manufacturing processes.

Today, with the accelerating complexity of nanoelectronics for memory applications, in-die overlay metrology has required much tighter control. A typical in-device overlay control strategy utilizes high-voltage SEM metrology across several key layers, but lot and wafer sampling is limited due to low system throughput. Our objective is to find a faster, more robust, and more efficient optical metrology solution that can produce the same in-die overlay results vs. SEM. In this work, we create a novel solution using the KLA SpectraShape 11k dimensional metrology system to demonstrate improved nonzero overlay (NZO) control that meets the tighter overlay budget requirement. We combined the spectroscopic Mueller matrix of SpectraShape 11k and the machine learning algorithm of TurboShape modeling software. Both real spectra collected by SpectraShape 11k and theoretical spectra generated from the scatterometry model are trained against their corresponding SEM reference and synthetic reference data respectively to predict the overlay value. Accurate and robust optical in-device overlay results are proven with a high correlation to the HV-SEM data. In addition, the SpectraShape 11k in-device overlay is equipped with a few key performance indicators (KPIs) including CIndex and CD profile, which are designed to flag process excursions in an HVM environment. Good agreement is observed between the KPIs and overlay delta to HV-SEM. Finally, the 4x-8x throughput advantage of optical metrology in-device overlay vs. SEM in-device overlay allows users to set more dense wafer measurements by lot or dense site measurements by wafer, enabling better lot-to-lot or wafer-to-wafer NZO control.

Semiconductor manufacturing relies on Critical Dimension Scanning Electron Microscopy (CD-SEM) for precision in resist pattern measurements. High-resolution CD-SEM images, while desirable, can damage the resist due to increased electron beam exposure with higher frame numbers. To address this, Noise2Noise, a deep-learning noise reduction method, is introduced. Noise2Noise employs multiple noise images for unsupervised noise reduction. However, it struggles with unknown samples and limited training data. This research enhances the Noise2Noise model by introducing Attention and Residual-Recurrent structures to extract high-precision images from low-resolution inputs (1 frame). The Attention-boosted Noise2Noise model in particular exhibits superior accuracy with improved Peak Signal-to-Noise Ratio (PSNR) and Structural Similarity (SSIM) for unseen patterns. Overall, the modeling error characterized by (ΔCD/CD) has been reduced compared to the conventional Noise2Noise method, promising improved CD-SEM accuracy for advanced CMOS manufacturing.

Semiconductor layer-to-layer overlay in manufacturing significantly impacts product quality and yield performance. Good control of device shifting also influences the spatial scale down for the nanoelectronics of memory applications. Advanced node DRAM semiconductor manufacturing requires a tighter in-die overlay budget. Typically, the inline overlay is measured by using a designed target in the scribe line. However, the difference between the metrology target and in-die device structure can lead to errors that can impact product quality and yield. This is especially true for complex structures such as the DRAM storage hole to landing pad overlay that cannot be well fabricated in the small target area. To meet the required tighter overlay control budget, the ability to measure in-die is essential. In this work, we introduce and demonstrate the line scan self-calibration solution for accurate and robust in-die overlay measurement of the storage node layer to the landing pad layer. Real spectra are collected by SpectraShape 11k dimensional metrology system where overlay splits are trained against the intended overlay and the SpectraShape 11k in-device overlay results are qualified by Set (designed overlay value from lithography), Get (overlay value measured by metrology tool) and TEM. Moreover, theoretical and experimental data show that the SpectraShape 11k Mueller elements are sensitive to tiny changes in the overlay parameters, which can enable robust, inline, high throughput overlay metrology. We demonstrate that the SpectraShape 11k successfully measures the in-die overlay of the complex storage hole to the landing pad structure with good accuracy and high throughput thereby contributing to improved process control and yield improvement.

This study introduces a novel self-adaptive Pattern-to-Pattern (P2P) inspection mode for wafer defect inspection. Different from the traditional Die-to-Die (D2D), Cell-to-Cell (C2C), and Die-to-Database (D2DB) inspection modes, the newly proposed P2P inspection mode has the advantages of no restriction on the inspection region and low dependence on image quality. It works with both SEM images and optical images from different inspection equipment. Using the design layout information, the inspection images are aligned with the design and divided into basic component patterns according to the geometric features of the design pattern. These components are then analyzed through similar pattern comparison to enable the inspection of unique and complex patterns. This self-adaptive method eliminates the influence of the manufacturing process variations by comparing aligned similar image patterns, thereby preventing the reporting of defects highly dependent on the inspection algorithm settings. To facilitate further analysis, a database of the basic pattern components is created by collecting extensive images along with corresponding design layout information.

Virtual metrology (VM) plays a pivotal role in enhancing productivity, improving quality, and reducing maintenance costs in semiconductor manufacturing by replacing traditional physical metrology. Many implementations of VM rely on the predictive modeling approach that leverages equipment sensor data to estimate crucial process outcome variables. Despite its inherent advantages, VM has not been deployed widely in actual manufacturing processes due to the lack of accuracy and scalability. Most machine learning algorithms struggle to effectively address practical challenges such as data drift, data shift, sparse ground-truth data, and inconsistent data quality prevalent in semiconductor manufacturing processes. To address these limitations, we introduce the aggregated adaptive online model (AggAOM), a novel approach that effectively tackles the challenge of data scarcity in VM. By leveraging the hierarchical structure of manufacturing equipment, AggAOM captures and utilizes the underlying commonalities among equipment chambers within the same hierarchy besides their individual variations. This methodology enables more efficient use of limited data and substantially improves the prediction accuracy of VM running in mega-fabs for high-volume manufacturing. We present the experimental results by utilizing the datasets collected from SK hynix over nine months and demonstrate that AggAOM outperforms existing models significantly in accuracy. This progress marks a significant step forward in optimizing VM for semiconductor manufacturing.

In semiconductor manufacturing process, thin film thickness must be precisely controlled. Because it requires fast and precise thickness measurement, studies have been conducted to analyze the thicknesses of thin films by applying deep learning algorithms to spectral reflectometry. The reflectance spectrum of a thin film sample, which varies according to the film thickness, can be calculated with well-known theoretical equation. A theoretical dataset being used to train a deep learning algorithm for thin film thickness analysis is generated by the theoretical equation. For the practical use of the trained deep learning algorithm, performance evaluation using actual measured data is essential, but it is not easy because the exact thickness of the film sample is not known. Recently, a study that proposed an uncertainty evaluation of thin film thickness measurement using a deep learning model by utilizing the certified reference materials (CRMs) was published. In this study, the measurement uncertainty of a deep learning algorithm for thin film thickness measurement using data augmentation was evaluated. Referring to previous studies, a multilayer perceptron algorithm was designed and trained by theoretical reflectance spectra of silicon dioxide thin film on silicon substrate with thin film thickness varying from 1 nm to 110 nm in visible band. Considering the intensity fluctuation of the light source used in the reflectometry, a noise with a normal distribution of 1% standard deviation was applied to the training dataset. Then, the reflectance spectrum of the silicon dioxide thin film CRMs measured in the wavelength range of 355 nm to 657 nm was analyzed with the trained model. Based on the thickness analysis results, a measurement uncertainty evaluation was performed by considering several uncertainty factors of the offset of the analysis result from the certified value, the uncertainty of the CRMs itself, and the measurement repeatability.

As the cell size of memory devices continues to shrink, tighter On-Product Overlay (OPO) specifications toward a 1nm OPO budget are required. EUV (extreme ultraviolet lithography) production was adopted in 2019 and the next lithography development known as High NA EUV will fulfill market demand beyond 5nm and 3nm process nodes. High NA EUV requires shrinking the scribe line from 50μm to 40μm, which results in new requirements for the target size to be smaller than the current size μDBO (16x16μm) and AIM (24x24μm) targets. The reduction in the scribe line is certainly beneficial to chipmakers for wafer real estate and yield. For metrology measurements in high-volume manufacturing (HVM), the main optical overlay (OVL) metrology usually uses imaging-based overlay (IBO) technology, while in other cases diffraction-based overlay (DBO) and scatterometry-based overlay (SCOL) are used. All methods (IBO, DBO, and SCOL) face the same challenge of target size reduction. For instance, IBO targets require a restricted number of grating bars. Most importantly, the smaller the target size, the less kernel information affects measurement quality. The spot size of DBO is larger than the target size, so it increases noise sources from the target's surroundings and affects the OVL accuracy. SCOL technology offers several advantages over IBO and DBO when measuring small targets since the spot size in SCOL is smaller and the spot navigation has a higher control mechanism. In this paper, we present a method called parallax to measure a single-cell overlay using pupil information. We will demonstrate three values: First, the target size can be reduced by up to half. Second, the measurement time is improved by saving navigation time from cell to cell. Third, the optical z-value for each point is reported along with OVL measurements. Additionally, the feasibility of single-cell OVL measurement and optical z-value is demonstrated as KPIs for process control.

The shrinking of device critical dimensions (CD) requires tighter control of critical dimension uniformity with every new device node. For propagating CD sampling recipes from process development to high-volume manufacturing (HVM), the number of sampled sites needs to be reduced. One of the largest challenges is the optimization of the measurement sample plan without sacrificing fingerprint quality. We developed a sampling optimization module that can predict the impact of CD downsampling on model quality and variability. Two modes of sampling optimization have been evaluated: rule-based (maximizing distances between sites) and data-based (keeping specific CD signatures intact). The optimized sampling plans can be exported or used inside the process control and monitoring software (OVALiS) to down-sample existing dense measurements and verify the performance on unseen datasets. We can rigorously simulate the effect of reduced sampling on CD dose correction and CDU control.

TSV (Through-Silicon Via) is a vertical interconnection structure achieved by creating holes in the silicon substrate of a chip. This paper explores the subtle differences in the reflection characteristics of light across various TSV structures. Electromagnetic simulation software, namely, Lumerical FDTD, based on the Finite-Difference Time-Domain (FDTD) method, was employed to establish electromagnetic models for TSV structures. 3D-FDTD simulations calculate near-field electromagnetic field data and derive near-field reflection spectra. The dataset comprises different TSV structures with varying critical dimensions (CD) and their corresponding far-field reflection spectra obtained through simulation. Our approach introduces two deep learning networks: the forward network and the inverse network. Given the time-consuming nature of FDTD electromagnetic simulation tools when dealing with complex structures, the forward network is trained to rapidly predict reflection spectrum signal data corresponding to CD parameters, effectively replacing simulation software. Using a threshold of 1% to determine the accuracy of the spectral predictions, forward prediction achieves 100% accuracy. Similarly, the inverse network is trained to predict the CD parameters of TSV structures from the reflection spectrum signal, allowing for fast and accurate inference of the dimensions of TSV structures and the extraction of geometric parameters. In reverse prediction, the MAPE (Mean Absolute Percentage Error) for R_top, height, and R_bot remains consistently below 5%.

As the semiconductor industry rapidly approaches lithography nodes beyond 3nm, On Product Overlay (OPO) becomes a critical factor in enabling process control and manufacturing yield. The correspondingly tight OPO error budget emphasizes the importance of accurate overlay (OVL) metrology for capturing and tracking ever-smaller processes and patterning variations. In the DRAM memory segment, additional challenges arise in layers around the storage node, where the critical patterning steps are on thick layers with denser patterns than on other layers. A major challenge for optical overlay measurement on storage node layers comes from opaque optical stack materials whose optical properties reduce signal penetration effectiveness. Another key challenge is the high aspect ratio between the stack height and the target pitch, reducing diffraction efficiency and sensitivity. IBO (Image-Based Overlay) studies have shown that long wavelength (WL) improves the measurability of thick layers and significantly improves overlay results. In this paper, it is reported that longer WL (>800nm) can overcome the measurability challenges and achieve accurate results on a DRAM storage node layer. We present how improvements in raw overlay signal (pupil-plane image uniformity) further result in Total Measurement Uncertainty (TMU) and residual improvements over previous baseline solutions. Long WL enables DRAM manufacturers to meet and tighten OPO specifications on thick, storage node layers in their advanced technology architectures.

The march towards miniaturization of semiconductor devices places strong constraints on metrology techniques. Effective process control for current and next-gen device manufacture demands characterization of complex three-dimensional structures, accurately, quickly, and preferably non-destructively. In isolation, no currently existing metrology technique can meet all these challenges. We present a hybrid metrology solution in the form of a Physics-Enabled AI system, based on the commercial software tool SandBox Studio AI. Through the integration of information from diverse metrology sources, the system adeptly generates detailed, high-fidelity 3D reconstructions and allows for the extraction of measurements from various planes within the structure, while minimizing measurement-related expenses and material waste. The method’s efficacy was demonstrated on two 3D structures: Gate-All-Around (GAA) FET and 3D NAND Slit, achieving sub-nm accuracy even with limited metrology input data.

The impact of mask defects on wafers has been successfully simulated by KLA’s mask SEM-to-Aerial (S2A) image simulator. The high prediction accuracy, high throughput and low cost have been proven by mask shop production users. S2A generates the reference mask SEM images by rendering the post-OPC design to match with measured mask SEM images containing defects. From the two mask SEM images, defect-free reference absorber contour and defective absorber contour are extracted, and the two contours are used for wafer-level aerial image simulation through EUV scanner conditions. Pass/Fail of %CDE, EPE, etc. are reported by automatically generating measurement cutlines. S2A can be used for wafer prediction for pre/post-repair full height absorber defects using top-down mask SEM images, but it cannot be used for EUV multi-layer buried defects or for partial height residues remaining after repair. KLA and SK hynix have been investigating a solution for this use case using AFM images, which can measure the height error from the buried defect or partial height residue in post-repair mask. In this paper, we will show how measured SEM and AFM images are processed to fit with rendered reference SEM and AFM images. We then show how advanced scanner simulation models are used for determining the wafer printability of mask absorber defects, buried defects and absorber residues. Finally, the predicted wafer impact of the mask defect is compared with wafer SEM images for validation. This approach, named S2A-3D, will help reduce loading on EUV actinic metrology and provide a fast, accurate and cost-effective dispositioning of post-repair EUV defects.

With the advancement of semiconductor device miniaturization, the critical dimension (CD) has reached several tens of nanometers. To meet high yield demands, strict CD control is crucial. However, conventional CD measurement methods such as SEM and scatterometry have a problem; the measurement time increases in proportion to the number of measurement points. To solve this problem, we have developed a CD measurement technology that enables high density measurement of more than 100,000 points on the wafer surface in a few minutes per wafer.1 The CD value is calculated from the correlation between the diffracted light signal and CD. Despite the advantages this method provides, there still have been challenges. Measuring the critical dimensions of resist patterns of several tens of nanometers formed in EUV lithography across the entire wafer sometimes poses difficulties due to insufficient sensitivity with diffracted light, making high-precision CD measurement difficult. In this paper, we propose an enhanced measurement technique that quantifies the changes in the polarization state of diffracted light and reflected light from the wafer as Stokes parameters and calculates the CD based on the correlation between the obtained Stokes parameters and the CD value. Theoretically, it is sensitive to resist patterns of a few nanometers. For accuracy verification, we measured next-generation DRAM process wafers, including EUV-processed wafers. The minimum of measurement error, which compared with the CD value measured by SEM, achieved to 3σ = 0.57. The total time for wafer measurement and calculation processing was about a few minutes per wafer for over 10,000 points on the wafer surface.

Advanced semiconductor devices target sub-2nm on-product overlay (OPO) and manufacturers utilize dense overlay (OVL) sampling and non-zero offset (NZO) control to enable such strict performance. Accurate optical OVL metrology systems with fast move-and-measurement (MAM) utilized at the after-develop inspection (ADI) step are required to support this OPO trend. This work presents an innovative Artificial Intelligence (AI) based, ultra-high-speed, overlay target focusing and centering approach on imaging-based overlay (IBO) measurements in the ADI step. The algorithm uses pre-trained image features and a deep learning model. The algorithm allows the measurement of every site across the wafer in its best centering and contrast focus position and thus overcomes intra-wafer process variations and enhanced measurement accuracy. The data will include results from multi-lot advanced DRAM process with basic performance analysis such as total measurement uncertainty (TMU), tool-to-tool matching (TTTM) and additional key performance indicators (KPIs).

Stochastic printing variations are a challenge for EUV lithography and it is well known that these variations worsen if exposed out-of-focus because the EUV image contrast degrades. The introduction of 0.55NA will improve image contrast at a reduced depth-of-focus. This paper will describe how best focus planes differences between features can be used to design focus-sensitive metrology targets that can report EUV focus if used in combination with an optical metrology tool. Moreover, the developed target methodology ensures design rules compliance. The focus metrology target concept is experimentally demonstrated using a 24nm pitch line/spacer in combination with a low-n EUV mask absorber material, metal-oxide-resist (MOR), and a 0.33NA EUV scanner. The observed focus variation is modeled to quantify how much content is correctable using scanner feedback. This illustrates that on-product focus metrology can improve focus performance if combined with advanced process control.

The accurate alignment between the reference layout, also known as the target pattern, and the scanning electron microscope (SEM) image is an essential undertaking in the die-to-database (D2DB) inspection within the semiconductor industry. In this study, we provide a novel approach that facilitates accurate pattern alignment between them by applying a generative adversarial network (GAN).

Advanced technology nodes require a thinner photoresist layer for patterning to prevent pattern collapse as feature sizes are tighter. Within this study, we delve into the impact of photoresist thickness thinning on metrology performance utilizing ASML's eP5 scanning electron microscope (SEM). A variety of eP5 SEM configurations and scanning methodologies were employed to assess SEM image quality and metrology precision. Additionally, the efficacy of line-space programmed defect (PD) detection was evaluated using distinct eP5 SEM settings. We note that achieving optimal metrology performance for distinct features might require to use of different SEM settings and scanning configurations. For instance, eP5 Quad-directional scan technique offers superior metrological results when compared to the unidirectional scan for the tip-to-tip (T2T) features. In the context of line-space PD inspection, lower e-beam landing energy is found to increase the sensitivity of bridge defect detection.

Pitch scaling of interconnects is required for 3D system integration with the industry shifting to bumpless bonding technology. However, hybrid metal/dielectric bonding requires tight process control of planarity after chemical mechanical polishing (CMP) to avoid bonding voids. Due to its sub-angstrom resolution, atomic force microscopy (AFM) is typically used to assess the nano-topography but conventional systems suffer from increased noise floor at high scanning speeds making it unsuitable for high-volume manufacturing (HVM). Here, we validate a novel in-line high-throughput AFM system (QUADRA) by reporting the topographical parameters of 250 nm and 1 μm size copper nano-pads at high scanning speeds that reach tens of wafers per hour throughput.

The next milestone in the resolution of high-volume manufacturing will be achieved by High-NA EUV Lithography (HiNA EUVL) systems. In addition to the development of high-NA EUV scanners, the implementation of next generation resist materials remains a critical challenge. Thinner resists are required to accommodate DoF decrease on higher NA physics, which may lead to e-beam metrology and e-beam inspection sensitivity loss due to less electron signal and more severe stochastic failures and variabilities. Due to worse resist imaging contrast and larger pattern roughness in HiNA EUVL, accurate and high resolution CD and defect metrology as well as precise process window (PW) evaluation which considers stochastic failure rate (FR) are needed for resist screening to support the gradual reduction of resist thickness. In this paper we present a thin resist evaluation flow based on next generation e-beam metrology tool (eP6), including metrology setup and qualification and stochastic-aware process window (SAPW) analysis. We will show ADI (after development imaging) evaluation results for a contact hole array with pitch of 32nm for three CAR resist deposited thicknesses from 60nm to 30nm (note: ~40% resist thickness loss post-development). First, we will illustrate some of the metrology responses associated with thin resist and highlight the benefits of improved precision (0.7x), resolution (1.5nm) and sensitivity of next generation metrology tool. For each resist thickness, we will show CD, LCDU and defect measurements across a focus-exposure matrix. LCDU decomposition will be used to quantify SEM, mask, and stochastic contributions to the total measured LCDU. Finally, we will exhibit the SAPW result (Dose-to-Size, Depth of Focus, Exposure Latitude … etc) for the range of resist thicknesses, which can be used to optimize process centering and qualify thin resist performance for HiNA with high correlation coefficient (> 0.9) between measured FR and modeled FR.

DRAM storage node profile measurement during high aspect ratio (HAR) etch has been one of the most challenging metrology steps. DRAM storage node profile affects refresh time and device electric quality. So, controlling this profile is one of the key challenges. Conventional 3D modeling in Optical Critical Dimension (OCD) metrology has typically used multiple cylinder stacks. This method cannot provide an accurate model and computed spectrum through the RCWA engine. This means we need a more accurate model. In this paper, we used hyper-profile to accurately measure a hole profile for better process control. Hyper-profile uses a polynomial to describe the smooth shape of a hole profile, which is much closer to the real product and provides a more accurate computed spectrum. With hyper -profile, a continuous storage node hole profile and managed CD correlation are achieved. It can maintain the same profile complexity with less degree of freedom, reducing the model uncertainty and ensuring more robust regression. On the other hand, as the metrology error budget becomes stricter and the process variation cycle is increasing, the OCD based model-guided machine learning (MGML) approach can provide a faster solution turnaround time with more accurate measurements than either pure OCD or pure ML approaches. It also can better decorrelate profile CDs and achieve more robust profile monitoring. In this paper, we will demonstrate the above benefits of hyper -profile and MGML in the DRAM storage node application.

One of the potential applications of coherent di raction imaging (CDI) methods is at-wavelength defect inspection of extreme ultraviolet (EUV) photomasks for future semiconductor technology nodes. Mask defect metrology requires very high resolution as the size of relevant defects is 10 nm or less. In CDI, the resolution is limited by the highest detectable diffraction frequency component. The diffraction signal generated by a small isolated defect drops quickly as the diffraction angle increases and often long integration times are required to achieve a useful signal to noise ratio. With the introduction of states-mixtures into CDI methods, which has been intensively developed in recent years, it is possible to relax the CDI coherence requirements, and thus increase the illumination flux and reduce the exposure time for several types of EUV sources. In this paper, we systematically study the limits of temporal coherence on CDI using EUV synchrotron light and imaging of EUV masks in the reflection mode and we quantify the potential throughput increase for EUV photomask metrology applications.

3D NAND flash memory stacks cells vertically in multiple layers. One of the critical processes in chip-making is slit trench landing control since the word-line gate replacement of silicon nitride films and the isolation of plural memory blocks are through the means of slit structure. However, during the gate of silicon nitride removal in slit trenches, the architecture of memory blocks may collapse due to the lack of sufficient supporting patterns surrounding the slit trenches. For better silicon nitride removal control, there are various irregular patterns of dummy pillars (PIL) designed in as supporting structures to provide better mechanical property, which can prevent memory blocks from collapsing while removing silicon nitride in gate replacement processing. Hence, an effective measurement is needed to indicate the bottom shifting of PIL during the etching recipe optimization. In this work, we demonstrate the deployment of small angle X-ray scattering (SAXS) technology with global tilt extraction (GTE) that successfully predicts PIL landing location displacement, which matches destructive gauging data. GTE is a modeless method to determine global tilt, i.e., center line shifting (CLS) of the bottom relative to the topmost on the target pattern. GTE is proven to be a reliable method for in-line process monitoring as well as for use in PIL etching recipe optimization for 3D NAND development.

On-product overlay (OPO) control in the DRAM process has become a critical component from node to node to produce high device yield. To meet OPO node goals, Non-Zero Offset (NZO) and its stability across lots must be monitored and controlled. NZO is the bias between overlay (OVL) on-target measurement at After Development Inspection (ADI) vs. on-device measurement at After Etching Inspection (AEI). In this paper, we will present Imaging-Based Overlay (IBO) metrology data at ADI of two different marks, segmented AIM® with design rule patterns and robust AIM (rAIM®) with Moiré effect with a small pitch. NZO analysis will be presented for each target type including basic performance.

EUV lithography enables continued scaling beyond 5nm nodes and allows the employment of single patterning methods with improved resolution. Thinner photo-resist layers with shrinking feature sizes consequently make stochastic errors worse during the lithography step and require a metrology solution with sub-nanometer resolution and information in the third dimension (depth and full profile shape). Atomic force microscopy (AFM), a topography imaging technique, can achieve the required precision to capture critical dimensions of photoresist patterns in 3 dimensions, but it is generally limited by the ability to fully resolve deep and narrow structures, can be destructive and suffer from low throughput. Here, we show validation of a novel fully automated in-line AFM system, QUADRA, that overcomes these challenges. Details relevant for use in HVM are reported on line and space EUV photoresist patterns after development (ADI).

3D NAND has become mainstream storage devices in a past decade and the stacking cell layers now reaches to more than 300 layers. As stack gets higher, more and more etching process challenges are brought into 3D NAND high aspect ratio (HAR) structure patterning. Among the HAR etching processes, the deep contact etches in the back-end-of-line (BEOL) are patterned after other HAR structures such as channel holes, deep trenches or other dummy patterns. Any unexpected overlapping of deep contacts with other patterns would lead to fatal product yield loss due to such wrong circuit connections and leakage currents. Hence, a reliable and fast monitoring methodology for profile tilting is extremely important. In this article, it is first time to demonstrate the employment of the small angle x-ray scattering (SAXS) technology and global tilt extraction (GTE) by using Axion @TM from KLA-Tencor to measure bottom tilting behavior for deep contact structure in 200+ layers of 3D NAND product. As regarding for the necessaries of gathering layout pitch, detail film stacks and hole dimensions by regular model base approach, the GTE is a pure modeless method by using x-ray scattering images to determine the central point shifting of the bottom relative to the topmost on the target pattern. With GTE help, the development cycle time for etch recipe tuning and BEOL process optimization is effectively improved, as well as demonstrating better process control to sustain product yield.

Semiconductor photocathodes are electron beam sources with versatile electron beam performance such as pulsed structure as well as high beam current with high monochromaticity. Photocathode using GaN semiconductor material has solved the durability problem, resulting in the development of a compact photocathode electron gun suitable for industrial technology. The photocathode electron gun can be retrofitted to existing electron microscopes, has the same brightness as a cold field emitter cathode, and the pulsed beam not only brings selective beam irradiation to arbitrary area in the field of view in SEM imaging, but also allows blur-free TEM imaging of moving samples.

Observation of high aspect ratio (HAR) structures is a difficult challenge in metrology and inspection in semiconductor manufacturing. In imaging HAR trenches using a scanning electron microscope (SEM), obtaining SEM images without information loss due to whiteouts and blackouts is challenging. One reason for the difficulty is that the probe current is constant in conventional SEM imaging. Suppose the probe current is increased to detect more secondary electrons from the bottom of the trench. In that case, excessive secondary electron emission from the top of the trench will result in a whiteout. The SEM equipped with a photocathode electron gun (PC-SEM) can change the probe current on a pixel-by-pixel basis by applying a pulsed electron beam. In this study, we propose two methods of SEM observation for HAR trenches. The first method uses a lower probe current at the top of the trench and a higher probe current at the bottom. With this method, the top and bottom of the trench could be observed simultaneously without any whiteout or blackout. Another method is to adjust the probe current so that the SEM image is in a constant grayscale. In this case, information about the sample appears in the probe current. The image of the probe current captured the trench bottom more clearly than the conventional SEM image under equivalent conditions.

With a sub-nanometric resolution required for nodes below 14 nm, according to the International Roadmap for Devices and Systems (IRDS), exploring new overlay characterization methods is key to drive further component size reduction and develop better-performing technologies. In this work, we present our first Small-Angle x-ray Scattering (SAXS) results of overlay measurements on stacks of silicon line gratings. Our method, novel for SAXS overlay measurements, is based on inverse problem resolution and reconstructs the in-depth profile (approximated as a stack of trapezoids) of the structure. We are thus able to extract overlay with SAXS with a very fine sensitivity, high precision and sub-nanometric resolution that suit the requirements for advanced technological nodes. We compared these results with those of Scanning Electron Microscopy (SEM) contour-based on product overlay. The reconstructed structures are compared to profiles obtained with Scanning Transmission Electron Microscopy (STEM). From the differences between these multi-scale techniques we can conclude on the high potential of SAXS to become a complementary to those existing, and assess its potential for advanced technology nodes.

The semiconductor manufacturing process is a complex and highly technical operation, demanding precise and consistent metrology throughout its prolonged duration. As manufacturing processes grow in complexity, it becomes imperative to measure key variables of the intermediate products. Consequently, there is an increased demand for higher throughput in metrology to enhance measurement capacity. The electron-beam (E-Beam) metrology tools can be accelerated by integrating denoiser models for image enhancement and reducing the sample rate of raw images. We propose a novel universal denoising method specifically tailored for the semiconductor industry. Distinct from traditional denoisers designed for standard cameras and the RGB space, our proposed solution is tailored to the nano-scale structures and noise patterns inherent in semiconductor images obtained via E-beam tools. To meet the strict precision requirements of semiconductor metrology, where even minimal deviations carry substantial implications, our approach introduces a specialized network structure with novel loss functions that reflect the unique characteristics of semiconductor metrology. We propose a novel conditioning scheme to apply a single trained model to diverse image domains from various wafer products and layers. By combining the proposed loss functions and conditioning scheme, we can universally handle multiple image domains with a single model. This method significantly reduces time expenditure while preserving the crucial accuracy necessary for high-quality semiconductor production. Through comprehensive volume testing across diverse metrology recipes, which covers the entire spectrum of DRAM fabrication, our method has demonstrated a notable increase in metrology throughput, achieving an average enhancement of 26%, and reaching up to 46%, all without compromising accuracy or reliability. This breakthrough offers a versatile and efficient solution, marking a significant advancement in the field of semiconductor manufacturing.

Edge placement error (EPE) has become a critically important metric in semiconductor manufacturing. EPE quantifies the difference between the designed and printed layout of devices, coupling overlay and critical dimension (CD) of different litho layers. EPE consists of global and local components and can manifest itself between different physical layers of a device (e.g., via, metal) or within a single layer (primarily relevant for multi-patterning). This paper will study the simplest case of a single layer using an N10 litho-etch-litho-etch (LELE) metal layer patterning and will mainly cover global EPE. Monitoring and control of EPE will enable the stability of integrated circuit devices in advanced technology nodes. Inline EPE prediction in the process control loop at previous litho and etch steps enables early wafer status diagnosis and process disposition, which will improve process margin and wafer yield. Overlay and CD are essential inputs for EPE monitoring, prediction and control. Direct measurement of EPE on the device provides a reference value for an EPE model with overlay and CD measured on special targets. KLA’s pattern-centric solutions provide unique and accurate functionality in EPE metrology by analyzing SEM images on devices or targets in combination with the chip design. In this paper, we conduct experiments for EPE modeling and perform reference analysis using KLA’s pattern-centric solutions, targeting a higher pass rate of e-test, lower defectivity and targeted SEM inspection. KLA’s pattern-centric solutions are applied to e-beam images and provide die-to-database analysis by extracting measurements. The resultant EPE analysis can provide a higher correlation between electrical test data and targeted hotspot inspection, and can also be used to build the EPE model, for example, using e-overlay or CD targets. Overall, the results of these studies show good agreement with EPE model predictions and measured EPE by KLA’s pattern-centric solutions on device structures.

In semiconductor industry, CD-SEMs (Critical Dimension Scanning Electron Microscopes) play a pivotal role in metrology and process control. Furthermore, additional applications harnessing the potential of CD-SEM equipment have been developed, including contour extraction algorithms, to address the increasing metrological demands. The task of detecting deformity in semiconductor processes has become a formidable challenge due to the continuous reduction in device feature sizes as we progress from one node to another. Deformity in this case can be described as simulation extra prints or detected manufacturing defects. In this paper, we have utilized vector calculations to detect deformity and calculate roughness. Our product, Calibre ContourCal, facilitates the computation of differences between lithographical simulations and measurements. By evaluating the Root Mean Square Error (RMSE) value, we can identify defects in the SEM image or unexpected extra prints in simulation. Additionally, we have proficiently positioned the sites in critical areas based on contour curvature. To evaluate the quality of the model’s simulated contours, we have introduced a novel indicator based on the difference between the simulated model's Power Spectral Density (PSD) and the fitted PSD. The computation of RMSE for a large FoV (Field of View) containing high site count, exceeding one million sites for example, is a demanding task. For that we parallelized our calculation method using GPUs. With the utilization of GPUs, we have achieved significant time savings, simplifying the processing of high site count. Consequently, we can efficiently detect deformity and calculate roughness for large FoV.

Critical dimension small angle X-ray scattering (CDSAXS) has been shown capable of measuring 3D NAND deep-etch structures, like channel holes and wordline cut for CD, CD profile, and center-line-shift (or tilt) non-destructively. New 3D NAND flash design architectures use taller stacks to increase memory capacity. Taller stacks result in deeper channel holes with aspect ratios exceeding 100:1. Etching high-aspect ratio holes remains the most critical step and requires a switch to cryogenic etch processes. This helps with throughput and lower cost, however, inner/outer hole loading, twisting, bowing, not open/partial etch can become more pronounced in low temperature processes. Reliable and non-destructive metrology is needed to address some of these challenges. In an effort to explore CDSAXS capability for this purpose, we report a systematic CDSAXS measurement study of 3D NAND channel hole etch for patterning and etch interaction in the following two aspects: 1) Patterning edge effects on the hole etch behavior, for CD, CD profile, tilt and distortion, specifically for holes at pattern edge (outer holes) and holes insider pattern (inner holes), and 2) hole etch behavior, especially versus etch depth, and its impact on the final hole pattern variance, e.g., pitch and hole-hole distance variance from the designed pattern (before etch). We study the patterning edge effects for a variety of process conditions and potential process optimization to minimize the edge effects. For hole etch pattern variance behavior, we focus on developing a feasible measurement methodology for characterizing the final etch pattern variance and potential metrology recipes.

Advances to smaller memory chip nodes has brought about challenges of accurately fabricating and monitoring increasingly narrow and high aspect ratio (HAR) features. Among these, the HAR etching process is considered the most critical and intricate step in the entire manufacturing flow. The production of high-quality HAR features require methodologies to tackle a range of process errors, including incomplete etching, bowing, twisting, tilting and CD variation. We present both theoretical insights and experimental evidence to highlight CD small-angle x-ray scattering (CDSAXS) as a powerful method for monitoring process variations such as tilt and bending signatures. This nondestructive approach holds immense potential as a rapid screening tool to detect etch process excursions. This method is model-free and eliminates the need for lengthy geometric-model-building processes that may take days to weeks. Moreover, it mitigates the risk of model failure and reduces engineering hours, making it a cost-effective and efficient solution.

Capacitors play an essential role in dynamic random-access memory (DRAM) devices. With continuous DRAM device scaling, critical dimension measurements and elemental analysis of capacitor structures becomes more critical. Here, we present an automated TEM metrology and EDS characterization workflow for plan view DRAM capacitors. We utilized a Metrios 6 (Scanning) Transmission Electron Microscope ((S)TEM) equipped with an Ultra-X Energy Dispersive X-Ray Spectroscopy (EDS) detector to obtain high-quality analytical information of DRAM capacitors. The large solid angle of the Ultra-X detector provides approximately 3-4 times more x-ray counts than the previous generation Dual-X detector. Further, we show Ultra-X detector can characterize the elemental composition even on layers as thin as ~1 nm using low electron doses. Additionally, we demonstrate that the extended EDS acquisition induces elemental diffusion and structural alterations, leading to a ~4% reduction in the radius of certain DRAM layers. These findings underscore the importance of controlling the electron dose during imaging to ensure accurate, reliable, and reproducible CD measurements.

SMILE is a free software for the analysis of line/space and contact/hole pattern images. The software is specifically designed to investigate SEM images of test structures for photoresist screening and to extract relevant metrics to assess the quality of the patterns. These metrics include the average critical dimension, the unbiased line edge roughness and the eventual presence of defects. This paper reviews the latest functionalities of SMILE, discusses the plans for future upgrades and includes a step by step workflow guide to use the software.

This study develops a parametric system transfer function (STF) model using scalar diffraction theory and Fourier optics to address the loss of precision in image-based positioning caused by the diffraction limit on marker scale. By fitting the model to observed STFs and employing deconvolution and a deep convolutional neural network, the method enhances image quality, overcoming traditional deconvolution limitations. Applied to critical dimension measurements, it improved radius accuracy for vias and pillars by 54.8% and reduced displacement measurement bias by 36.4%. The development particularly benefits automatic optical inspection (AOI) for quality control in semiconductor manufacturing.

Dose and focus are both primary contributors to a change in feature size (critical dimension – CD). Within the context of this abstract, dose refers to all ‘apparent dose’ effects within the scanner and track combination. These dose-like effects can be an actual dose from the scanner and/or an apparent dose coming from process effects (i.e. resist/develop nonuniformity) that impact CD’s in a manner similar to scanner dose. Semiconductor manufacturers monitor CD over time for process control and can institute dose and/or focus changes in order to maintain CD performance and to optimize CD uniformity. This CD monitoring and control can be time consuming and a shift in CD does not directly indicate which has changed, dose or focus. Until now there is not a good alternate way to detect and monitor dose-related changes on product wafers. This paper will introduce a dual tone target concept for dose metrology to distinguish CD changes from dose and focus and demonstrate how the dual tone target concept is used to infer the apparent dose on a diffraction-based optical metrology system, like YieldStar. The concept is verified via experimental results showing accurate dose measurements with low focus cross talk. Additionally, correlation with CD-SEM measurements will be demonstrated which shows that apparent dose derived from this diffraction-based methodology matches well to the CD-SEM.

3D flash memory structures have been rapidly developed over the past decade to achieve a high density of stacked memory cells with periodic channel holes across the device. Small deviations of the hole shape can result in considerable variations in device performance and product yield. Understanding the behavior and performance of these high-aspect-ratio structures plays a vital role in such complex vertically stacked structures. Memory hole critical dimensions (CDs) serve as the key information to evaluate the performance of 3D flash memory devices, and these CDs are typically measured by rigorous coupled wave analysis (RCWA) based optical metrology that requires costly and destructive scanning electron microscopy (SEM) or transmission electron microscopy (TEM) reference. Here, we utilize critical dimension smallangle x-ray scatterometry (CD-SAXS) that provides reliable and nondestructive ground truth reference to extract a large amount of detailed hole shape information within a practical time scale compared to traditional lengthy TEM measurements. We leverage advanced data analytics and machine learning techniques to enable an optical critical dimension metrology solution along with the desired amount of reference from CD-SAXS measurements for the memory hole profile investigation. This proposed methodology opens up a new venue for a high-throughput, robust and accurate hole CD profile measurement for the fast-paced and high-volume 3D flash memory manufacturing technology.

In semiconductor manufacturing process, identification of device defects in early phase of the process flow is critical for accelerate process ramp-up times. On the other hand, the number of invisible electrical and material defects which cannot be detected by conventional dimensional metrology is increasing as semiconductor devices become more complex. To overcome this difficulty, we have developed an SEM equipped with two features: an electron beam modulator to generate pulsed electron beam and a laser irradiation feature. The laser enables control of the electrical state while the electron beam modulation enables charge dynamics measurement of device elements. In this report, we present (1) a technique to improve the detection sensitivity of contact defects by utilizing wavelength tunability and (2) evaluation results of contact resistance from voltage contrast using RC estimation systems.

To maintain lithographic pitch scaling, extreme ultraviolet (EUV) processes have been adopted in high-volume manufacturing (HVM) for today’s advanced logic and memory devices. Among various defect sources, stochastic patterning defects are one of the most important yield detractors for EUV processes. In this work, we will limit our scope to patterning defects arising out of lithography. In the past, it has been shown that the patterning defect process window is often limited by stochastic hotspots. These hotspots have very low failure probabilities in a well-optimized process, and hence their detection necessitates large area sensitive defect inspection, such as with a broadband plasma (BBP) optical defect inspection system. It has also been shown that systematic issues in design can be exacerbated by stochastic variations. Hence, it is critical to discover these hotspots and study their variability with massive SEM metrology. Such analyses can uncover systematic trends, which can then be corrected and monitored. In this work, we discover hotspots using broadband plasma (BBP) optical inspection and study their variability using KLA’s aiSIGHT™ pattern-centric defect and metrology software solution for automatic defect classification and SEM metrology measurements. We also demonstrate the need for fast and rigorous 3D probabilistic stochastic defect detection on design as a continuation of this work.

Process control of advanced semiconductor nodes is not only pushing the limits of metrology equipment requirements in terms of resolution and throughput but also in terms of the richness of data to be extracted to enable engineers to finetune the process steps for increased yield. The move towards 3D structures requires extraction of critical dimension parameters from structures which can vary largely from layer to layer. For in-line process control, the necessary automation forces the development of layer and equipment-specific dedicated image processing algorithms. Similarly, with the increase in stochastic defects in the EUV era, detection of defects at the nm scale requires the identification of features captured in low resolution to meet the throughput requirements of HVM fabs, which can again lead to custom algorithm development. With the emergence of ML-based image processing methods, this process of algorithm development for both cases can be accelerated. In this work, we provide the general framework under which the images obtained from high-speed scanning probe microscopy-based systems can be used to train a network for either feature detection for parameter extraction or defect identification.

Advanced semiconductor nodes are pushing the limits of feature sizes and require metrology with sub-nm resolution without compromising on the throughput as needed for in-line process control. Recently, high-throughput scanning probe microscopy (SPM) based metrology and inspection tools capable of meeting these needs have been introduced to the market and qualified for use in HVM. While innovative measurement methods and tool architecture have allowed for a leap of improvement in throughput, the next step in further reducing imaging time can be obtained through the application of machine learning for enhancing the resolution of measured images for extraction of relevant parameters. In this work, we provide the general framework under which a neural network-based resolution enhancer is designed and used for SPM images. We showcase the effectiveness of this framework using measurements performed on Line/Space structures with a pitch of 200 nm. For the reusability of a pre-developed pre-trained model, we additionally leverage transfer learning and show that a new model for slightly differing structures can be re-trained and calibrated with a smaller data set of measurements performed on Line/Space structures with a pitch of 100 nm.

Wafer overlay errors due to non-flatness and thickness variations of a mask need to be minimized to achieve a very accurate on-product-overlay (OPO). Due to the impact of overlay errors inherent in all reflective lithography systems, EUV reticles will need to adhere to flatness specifications below 10nm, which metric is not possible to achieve using current tooling infrastructure; current metric is showing Peak-to-Valley (PV) flatness of around 60nm. In this paper, we present a new method to generate a very high-resolution photomask shape measurement of an entire optical photomask used in DUV lithography, by measuring both from front side and backside, a technique based on detecting the wave front phase of the reflected light from a quartz photomask. We introduce Wave Front Phase Imaging (WFPI), a new method for measuring flatness that generates a shape map based on local slope. It collects 810 thousand (K) data points on an 86.4mm× 86.4mm area with a spatial resolution of 96μm.

Performing accurate and timely Scanning Electron Microscope (SEM) image analysis to identify wafer defects is crucial as it directly impacts manufacturing yield. In this paper, a machine learning (ML) based approach for analyzing SEM images (from wafer inspection machines) to locate and classify wafer defects is proposed. A state-of-the-art one-stage objection detection model called YOLOv8 (You Only Look Once version 8) is used as it offers a good balance between accuracy and inference speed. Experimental results confirm that an ensemble model composed of multiple YOLOv8 models can predict 6 types of defects with a mean Average Precision (mAP) of 0.789 (at IoU=0.5) for unseen test data consisting of real-world SEM images from 5 wafer fabs that have varying image qualities.

We present a contour metrology-based process matching flow with machine learning-based site selection for best coverage, contour comparisons, and scoring to quantify process differences. This method can significantly improve the efficiency of process technology transfers between fabs. The key technology includes: 1) high-performance ML clustering on a full chip product with hundreds of millions of anchoring points, 2) process-matching oriented custom feature engineering that drives quantitative understanding of each SEM image, and 3) stable and reliable contour extraction of large amounts of CD-SEM images.

Multi-wavelength (MWL) micro diffraction-based overlay (μDBO) is a prominent method for after-develop inspection (ADI) overlay measurements, which is favorable for accuracy and robustness. Continuous-bias DBO (cDBO) is expected to offer robustness improvements against stack variation, asymmetry, and imbalance. In this paper, dual-WL (DWL) cDBO profiles were evaluated to secure the advantages of both of MWL and cDBO applications. The metrics used to evaluate accuracy and robustness of ADI overlay measurements are residual, dynamic precision (DP), and wafer-to-wafer variation of the difference between ADI and after-etch inspection overlay. 70% of DWL profiles had improvements in their residual values comparing with their single-WL (SWL) constituents on Samsung R&D wafers in layer A. On layer B, the best DWL cDBO profiles showed around 5% improved residuals comparing with its SWL constituents. DWL cDBO showed around 30% averaged improved DP compared with SWL counterparts. DP improvements of MWL cDBO are following the expected DP improvements, based on the signal-to-noise ratio improvement with increasing number of signals. Residual improvement with increasing number of WLs is different from the DP improvement, and the best DWL residual improvement is higher than that of SWL measurements with noise reduction techniques applied. This shows that the residual improvement cannot be attributed to the increased number of acquisitions, and that it could be an innate advantage of MWL cDBO.

In the pursuit of high yield on semiconductor production with shrinking device features and complex 3D structures, defect inspection and root cause analysis are critical for yield learning. While top-down SEM-imaging of E-beam inspector provides an estimate of wafer defectivity, root cause analysis reveals the ground truth for the defects captured by E-beam inspector. A large variety of defect types are present for different devices, such as memory (ex. 3D NAND, DRAM), logic, or MEMS. Defect root cause analysis is necessary for all. Traditionally, defect root cause analysis has been completely manual, which is both cumbersome and time-consuming for engineers. This poster introduces the pivotal and innovative workflow on a DualBeam that automates every step of Defect Root Cause Analysis, from defect navigation, mill preparation, milling to final imaging of defect cross section. This new technology provides analysis that is: precisely on defect; vertically milled on a deep structure; planar across the defect plane; and crisply SEM imaged on the cross section. This paper also discusses the two automatic workflows of achieving Defect Root Cause Analysis. Deep mill exposes a cross section designed for fast turnaround time (TAT) of high aspect ratio devices defect analysis with high resolution SEM images, while piece extraction provides an easy TEM sample preparation method for intensive defect analysis. Both methods allow wafers to stay in the fab instead of breaking wafers for the lab environment.

With the increasing complexity of semiconductor manufacturing processes, from early R&D through ramp and high-volume manufacturing (HVM), a myriad of data analysis solutions are required for fast and actionable decisions in a fab. In our previous work, we used the SEM metrology capabilities of aiSIGHT to perform shape analysis and defect detection of contact holes and pillars in tight-pitch DRAM structures such as storage node landing pad arrays (SNLP) to gain insights on process variability. This paper focuses on a different type of metrology application, extracting unbiased roughness from mask and wafer SEM images, such as unbiased line edge roughness (LER) and line width roughness (LWR), along with defect detection.

Extreme Ultraviolet lithography with a numerical aperture of 0.55 will bring an improved optical contrast for contact hole layers and via layers. This improved optical contrast should lead to a reduction in the number of stochastic defects for these layers. To quantify this reduction, an adequate inspection methodology is required that can detect, in addition to the standard missing and merging defects, contact holes that are only partially opened. In this work we demonstrate a technique that uses backscattered electrons to detect these defects. In the first phase the beam-settings in a top-down scanning electron microscope are optimized to visualize holes that have been confirmed to be partially opened contact holes by either voltage contrast or transmission electron microscope. In the second phase these beam conditions are implemented on a massive metrology e-beam tool that has an increased throughput and therefore can collect information on millions of contact holes. In the last phase we show how this inspection can be used to enlarge the failure free latitude on a 36nm hexagonal contact hole pattern and to optimize the litho and etch conditions to minimize the number of stochastic defects on product wafers.

The semiconductor industry has been largely using the mean+3sigma overlay dispositioning metric for over 20 years now. As technology shrink progresses, this metric does not represent the most accurate overlay condition on the wafer. The continuous usage of the traditional metric leads to non-optimal rework decisions and potential yield loss in high-volume manufacturing (HVM). We propose an alternative overlay dispositioning metric that reduces rework without compromising accuracy or sampling. The proposed metric is called ‘number-of-dies-within-spec’. It is obtained by first evaluating the overlay model on a dense grid, followed by comparing the grid values against the spec limits. Based on that, each die can be evaluated, and dies below the spec are counted to obtain the wafer key performance indicator (KPI) “number-of-dies-within-spec”. This paper shows the rework gain for two layers when using our proposed metric against the traditional mean+3sigma dispositioning.

This paper introduces our development of software designed for OCD (Optical Critical Dimension) modeling, utilizing 3D graphics design functionality. In the OCD metrology, the role of analysis software is crucial for accurately and precisely extracting CD parameters from intricate device structures. Our software incorporates calculation engines grounded in Physics and Machine Learning - RCWA (Rigorous Coupled Wave Analysis) and DL (Deep Learning). The software's advanced 3D modeling engine supports complex structure manipulation and precise adjustments of a broad range of parameters, including optical properties. This facilitates detailed device geometry exploration through a cohesive interface. The DL algorithm has been developed ensuring consistency between RCWA and DL predictions, essential for accurate and rapid OCD metrology. We have conducted a comprehensive evaluation process to assess the consistency between RCWA calculations and 3D representations, encompassing both 2D and 3D structures. Further evaluation is planned, specifically focusing on real patterned wafers.

In the face of the escalating challenges posed by Moore's Law, semiconductor manufacturers find themselves compelled to explore innovative techniques aimed at enhancing the density of chip components. The reduction in pitches to sizes below 32nm and the adoption of advanced semiconductor packaging technologies have become common strategies. However, this evolution in chip architecture has led to an increase in nano-scale defects, necessitating the development of an ADCD framework. Yet, the scarcity of comprehensive data for training inspection models impedes progress. SEM imaging and manual defect labelling are resource-intensive, and the sensitivity of wafer images precludes data sharing among different foundries/users/manufacturers. Moreover, the variability in defect classes and occurrences across different clients further complicates the development of a universally applicable model. To address these challenges, we propose a decentralized Federated Learning framework utilizing the YOLOv8 object detection model. By securely leveraging the diverse datasets among participants without exchanging sensitive information, our approach aims to create a more generalizable model.